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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-unmerge-values.mir	14 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64) 26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 30 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0 1144 %3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2 1188 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), … 1192 … CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), … 1196 … CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), … 1200 … CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), … 1236 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[… 1245 …; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [… [all …]
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-unmerge-values.mir	14 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64) 26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 30 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0 1145 %3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2 1189 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), … 1193 … CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), … 1197 … CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), … 1201 … CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), … 1237 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[… 1246 …; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [… [all …]
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-unmerge-values.mir	14 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64) 26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 30 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0 1145 %3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2 1189 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), … 1193 … CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), … 1197 … CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), … 1201 … CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), … 1237 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[… 1246 …; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [… [all …]
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-unmerge-values.mir	14 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64) 26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 30 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0 1144 %3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2 1188 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), … 1192 … CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), … 1196 … CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), … 1200 … CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), … 1236 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[… 1245 …; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [… [all …]
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-unmerge-values.mir	14 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64) 26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 30 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0 1145 %3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2 1189 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), … 1193 … CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), … 1197 … CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), … 1201 … CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), … 1237 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[… 1246 …; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [… [all …]
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-unmerge-values.mir	14 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64) 26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 30 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0 1145 %3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2 1189 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), … 1193 … CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), … 1197 … CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), … 1201 … CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), … 1237 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[… 1246 …; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [… [all …]
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-unmerge-values.mir	14 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64) 26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 30 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0 1144 %3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2 1188 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), … 1192 … CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), … 1196 … CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), … 1200 … CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), … 1236 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[… 1245 …; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [… [all …]
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-unmerge-values.mir	14 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64) 26 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) 30 %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0 1145 %3:_(<3 x s32>), %4:_(<3 x s32>), %5:_(<3 x s32>), %6:_(<3 x s32>) = G_UNMERGE_VALUES %2 1189 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), … 1193 … CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), … 1197 … CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), … 1201 … CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), … 1237 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[… 1246 …; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [… [all …]
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	legalize-inserts.mir	220 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 225 ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) 230 ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32) 231 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32) 236 ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR1]](s32) 242 ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR2]](s32) 248 ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[OR3]](s32) 254 ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[OR4]](s32) 260 ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[OR5]](s32) 274 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[OR7]](s32) [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/GlobalISel/
H A D	legalize-inserts.mir	220 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 225 ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) 230 ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32) 231 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32) 236 ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR1]](s32) 242 ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR2]](s32) 248 ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[OR3]](s32) 254 ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[OR4]](s32) 260 ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[OR5]](s32) 274 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[OR7]](s32) [all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	legalize-inserts.mir	220 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 225 ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) 230 ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32) 231 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32) 236 ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR1]](s32) 242 ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR2]](s32) 248 ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[OR3]](s32) 254 ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[OR4]](s32) 260 ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[OR5]](s32) 274 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[OR7]](s32) [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	legalize-inserts.mir	220 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 225 ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) 230 ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32) 231 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32) 236 ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR1]](s32) 242 ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR2]](s32) 248 ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[OR3]](s32) 254 ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[OR4]](s32) 260 ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[OR5]](s32) 274 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[OR7]](s32) [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	legalize-inserts.mir	220 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 225 ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) 230 ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32) 231 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32) 236 ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR1]](s32) 242 ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR2]](s32) 248 ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[OR3]](s32) 254 ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[OR4]](s32) 260 ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[OR5]](s32) 274 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[OR7]](s32) [all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-implicit-def-s1025.mir	11 …s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s3… 15 ; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32) 17 ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 21 ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32) 22 ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 26 ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32) 27 ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 31 ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32) 32 ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32) 36 ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32) [all …]
/dports/security/libzrtpcppcore/ZRTPCPP-4.6.6/bnlib/ec/
H A D	curve25519-donna.c	102 output[0] = ((limb) ((s32) in2[0])) * ((s32) in[0]); in fproduct() 104 ((limb) ((s32) in2[1])) * ((s32) in[0]); in fproduct() 107 ((limb) ((s32) in2[2])) * ((s32) in[0]); in fproduct() 266 static s32 div_s32_by_2_25(const s32 v) in div_s32_by_2_25() 309 s32 over32 = div_s32_by_2_25((s32) output[1]); in freduce_coefficients() 439 const s32 mask = (s32)(input[i]) >> 31; in fcontract() 444 const s32 mask = (s32)(input[i]) >> 31; in fcontract() 451 const s32 mask = (s32)(input[9]) >> 31; in fcontract() 469 const s32 mask = (s32)(input[0]) >> 31; in fcontract() 580 const s32 swap = (s32) -iswap; in swap_conditional() [all …]
/dports/security/p5-Crypt-Curve25519/Crypt-Curve25519-0.06/
H A D	curve25519-donna.c	102 output[0] = ((limb) ((s32) in2[0])) * ((s32) in[0]); in fproduct() 104 ((limb) ((s32) in2[1])) * ((s32) in[0]); in fproduct() 107 ((limb) ((s32) in2[2])) * ((s32) in[0]); in fproduct() 111 ((limb) ((s32) in2[3])) * ((s32) in[0]); in fproduct() 312 s32 over32 = div_s32_by_2_25((s32) output[1]); in freduce_coefficients() 442 const s32 mask = (s32)(input[i]) >> 31; in fcontract() 447 const s32 mask = (s32)(input[i]) >> 31; in fcontract() 454 const s32 mask = (s32)(input[9]) >> 31; in fcontract() 472 const s32 mask = (s32)(input[0]) >> 31; in fcontract() 582 const s32 swap = (s32) -iswap; in swap_conditional() [all …]

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