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Searched refs:s_xor_b64 (Results 1 – 25 of 935) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dssubsat.ll58 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
82 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
96 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
143 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
150 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
206 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
213 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
220 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
283 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
290 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
H A Dscalar-branch-missing-and-exec.ll7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
10 ; The problematic case is s_xor_b64, as, unlike the other ops, it can actually
13 ; The check for an s_xor_b64 is just to check that this test tests what it is
14 ; supposed to test. If the s_xor_b64 disappears due to some other case, it does
20 ; CHECK: s_xor_b64
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dssubsat.ll58 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
82 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
96 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
143 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
150 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
206 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
213 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
220 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
283 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
290 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dssubsat.ll58 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
82 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
96 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
143 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
150 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
206 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
213 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
220 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
283 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
290 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dssubsat.ll67 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
96 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
108 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
161 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
168 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
230 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
237 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
244 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
314 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
321 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
H A Dscalar-branch-missing-and-exec.ll7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
10 ; The problematic case is s_xor_b64, as, unlike the other ops, it can actually
13 ; The check for an s_xor_b64 is just to check that this test tests what it is
14 ; supposed to test. If the s_xor_b64 disappears due to some other case, it does
20 ; CHECK: s_xor_b64
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dssubsat.ll69 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
100 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
114 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
168 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
175 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
238 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
245 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
252 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
323 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
330 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
H A Dscalar-branch-missing-and-exec.ll7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
10 ; The problematic case is s_xor_b64, as, unlike the other ops, it can actually
13 ; The check for an s_xor_b64 is just to check that this test tests what it is
14 ; supposed to test. If the s_xor_b64 disappears due to some other case, it does
20 ; CHECK: s_xor_b64
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dssubsat.ll69 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
100 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
114 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
168 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
175 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
238 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
245 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
252 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
323 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
330 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dssubsat.ll69 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
100 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
114 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
168 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
175 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
238 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
245 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
252 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
323 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
330 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dssubsat.ll69 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
100 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
114 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
168 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
175 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
238 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
245 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
252 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
323 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
330 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
[all …]
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
H A Dscalar-branch-missing-and-exec.ll7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
10 ; The problematic case is s_xor_b64, as, unlike the other ops, it can actually
13 ; The check for an s_xor_b64 is just to check that this test tests what it is
14 ; supposed to test. If the s_xor_b64 disappears due to some other case, it does
20 ; CHECK: s_xor_b64
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]
H A Dscalar-branch-missing-and-exec.ll7 ; v_cmp results being combined together with s_and_b64, s_or_b64 and s_xor_b64,
10 ; The problematic case is s_xor_b64, as, unlike the other ops, it can actually
13 ; The check for an s_xor_b64 is just to check that this test tests what it is
14 ; supposed to test. If the s_xor_b64 disappears due to some other case, it does
20 ; CHECK: s_xor_b64
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dcc-sgpr-limit.ll97 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[2:3]
98 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[4:5]
99 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[6:7]
100 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[8:9]
101 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[10:11]
102 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[12:13]
103 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[14:15]
104 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[16:17]
105 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[18:19]
106 ; CHECK: s_xor_b64 s[0:1], s[0:1], s[20:21]
[all …]

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