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/dports/devel/plan9port/plan9port-1f098efb7370a0b28306d10681e21883fb1c1507/src/cmd/astro/
H A Dsatel.c31 char **satp; in satels() local
34 satp = satlst; in satels()
37 if(*satp == 0) in satels()
39 f = open(*satp, 0); in satels()
41 fprint(2, "cannot open %s\n", *satp); in satels()
42 satp += 2; in satels()
45 satp++; in satels()
107 if((*satp)[0] == '-') in satels()
108 event("%s pass at ", (*satp)+1, "", in satels()
110 event("%s pass at ", *satp, "", in satels()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/
H A Dmonitor.c154 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; in mem_info_svxx()
155 vm = get_field(env->satp, SATP32_MODE); in mem_info_svxx()
157 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; in mem_info_svxx()
158 vm = get_field(env->satp, SATP64_MODE); in mem_info_svxx()
224 if (!(env->satp & SATP32_MODE)) { in hmp_info_mem()
229 if (!(env->satp & SATP64_MODE)) { in hmp_info_mem()
/dports/emulators/qemu/qemu-6.2.0/target/riscv/
H A Dmonitor.c154 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT; in mem_info_svxx()
155 vm = get_field(env->satp, SATP32_MODE); in mem_info_svxx()
157 base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT; in mem_info_svxx()
158 vm = get_field(env->satp, SATP64_MODE); in mem_info_svxx()
224 if (!(env->satp & SATP32_MODE)) { in hmp_info_mem()
229 if (!(env->satp & SATP64_MODE)) { in hmp_info_mem()
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Dmmu.h496 inline vm_info decode_vm_info(int xlen, bool stage2, reg_t prv, reg_t satp) in decode_vm_info() argument
501 switch (get_field(satp, SATP32_MODE)) { in decode_vm_info()
503 case SATP_MODE_SV32: return {2, 10, 0, 4, (satp & SATP32_PPN) << PGSHIFT}; in decode_vm_info()
507 switch (get_field(satp, SATP64_MODE)) { in decode_vm_info()
509 case SATP_MODE_SV39: return {3, 9, 0, 8, (satp & SATP64_PPN) << PGSHIFT}; in decode_vm_info()
510 case SATP_MODE_SV48: return {4, 9, 0, 8, (satp & SATP64_PPN) << PGSHIFT}; in decode_vm_info()
511 case SATP_MODE_SV57: return {5, 9, 0, 8, (satp & SATP64_PPN) << PGSHIFT}; in decode_vm_info()
512 case SATP_MODE_SV64: return {6, 9, 0, 8, (satp & SATP64_PPN) << PGSHIFT}; in decode_vm_info()
516 switch (get_field(satp, HGATP32_MODE)) { in decode_vm_info()
522 switch (get_field(satp, HGATP64_MODE)) { in decode_vm_info()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/devel/llvm11/llvm-11.0.1.src/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
H A Ddeprecated-csr-names.s65 # CHECK-INST: csrrw zero, satp, zero
67 # CHECK-INST-ALIAS: csrw satp, zero
69 # CHECK-INST: csrrw zero, satp, zero
71 # CHECK-INST-ALIAS: csrw satp, zero
/dports/devel/llvm10/llvm-10.0.1.src/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
H A Ddeprecated-csr-names.s65 # CHECK-INST: csrrw zero, satp, zero
67 # CHECK-INST-ALIAS: csrw satp, zero
69 # CHECK-INST: csrrw zero, satp, zero
71 # CHECK-INST-ALIAS: csrw satp, zero
/dports/devel/llvm90/llvm-9.0.1.src/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
H A Ddeprecated-csr-names.s65 # CHECK-INST: csrrw zero, satp, zero
67 # CHECK-INST-ALIAS: csrw satp, zero
69 # CHECK-INST: csrrw zero, satp, zero
71 # CHECK-INST-ALIAS: csrw satp, zero
/dports/devel/llvm80/llvm-8.0.1.src/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
H A Ddeprecated-csr-names.s65 # CHECK-INST: csrrw zero, satp, zero
67 # CHECK-INST-ALIAS: csrw satp, zero
69 # CHECK-INST: csrrw zero, satp, zero
71 # CHECK-INST-ALIAS: csrw satp, zero
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
H A Ddeprecated-csr-names.s65 # CHECK-INST: csrrw zero, satp, zero
67 # CHECK-INST-ALIAS: csrw satp, zero
69 # CHECK-INST: csrrw zero, satp, zero
71 # CHECK-INST-ALIAS: csrw satp, zero
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/RISCV/
H A Dsupervisor-csr-names.s181 # satp
183 # CHECK-INST: csrrs t1, satp, zero
185 # CHECK-INST-ALIAS: csrr t1, satp
187 # CHECK-INST: csrrs t2, satp, zero
189 # CHECK-INST-ALIAS: csrr t2, satp
191 csrrs t1, satp, zero
/dports/net-p2p/c-lightning/lightning-0.10.2/common/test/
H A Drun-amount.c79 #define FAIL_SAT(satp, str) \ argument
80 assert(!parse_amount_sat((satp), (str), strlen(str)))
81 #define PASS_SAT(satp, str, val) \ argument
83 assert(parse_amount_sat((satp), (str), strlen(str))); \
84 assert((satp)->satoshis == val); \
/dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/
H A Dmonitor.c153 base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; in mem_info_svxx()
155 vm = get_field(env->satp, SATP_MODE); in mem_info_svxx()
223 if (!(env->satp & SATP_MODE)) { in hmp_info_mem()

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