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Searched refs:sclk_d1 (Results 1 – 1 of 1) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300.v509 reg sclk_d1; register
512 always @(posedge radio_clk) sclk_d1 <= DB_DAC_SCLK;
521 else if(~DB_DAC_SCLK & sclk_d1)
526 else if(bitcount == 0 & DB_DAC_SCLK & ~sclk_d1)