| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1679 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1743 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1744 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1756 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1757 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1758 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1910 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1911 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1913 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1914 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1679 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1743 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1744 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1756 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1757 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1758 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1910 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1911 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1913 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1914 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1679 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1743 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1744 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1756 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1757 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1758 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1910 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1911 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1913 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1914 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1679 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready;
1743 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */
1744 rd_sample = cl_val + 2 * sdr_cycle_incr;
1756 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE;
1757 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES;
1758 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES;
1910 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */
1911 rd_sample = cl_val + 2 * sdr_cycle_incr;
1913 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES;
1914 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES;
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1677 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; in mv_ddr_rl_dqs_burst() local
1741 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1742 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1754 sdr_cycle_incr = i % TAPS_PER_RD_SAMPLE; in mv_ddr_rl_dqs_burst()
1755 rl_adll_val = sdr_cycle_incr % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1756 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1908 sdr_cycle_incr = i / TAPS_PER_RD_SAMPLE; /* sdr cycle increment */ in mv_ddr_rl_dqs_burst()
1909 rd_sample = cl_val + 2 * sdr_cycle_incr; in mv_ddr_rl_dqs_burst()
1911 min_phase = (rl_min_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
1912 max_phase = (rl_max_val[effective_cs] - (sdr_cycle_incr * TAPS_PER_RD_SAMPLE)) % MAX_RD_SAMPLES; in mv_ddr_rl_dqs_burst()
[all …]
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