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Searched refs:selection_vars (Results 1 – 5 of 5) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/passes/cmds/
H A Ddesign.cc347 design_copy->selection_vars = design->selection_vars; in execute()
365 design->selection_vars.clear(); in execute()
392 design->selection_vars = saved_design->selection_vars; in execute()
H A Dselect.cc558 if (design->selection_vars.count(str) > 0) { in select_op_expand()
559 for (auto i1 : design->selection_vars.at(str).selected_members) in select_op_expand()
761 if (design->selection_vars.count(set_name) > 0) in select_stmt()
762 work_stack.push_back(design->selection_vars[set_name]); in select_stmt()
1558 design->selection_vars[set_name] = RTLIL::Selection(false); in execute()
1560 design->selection_vars[set_name] = work_stack.back(); in execute()
1566 if (!design->selection_vars.erase(unset_name)) in execute()
/dports/cad/yosys/yosys-yosys-0.12/passes/techmap/
H A Dabc9_ops.cc442 auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false))); in prep_dff()
/dports/cad/yosys/yosys-yosys-0.12/kernel/
H A Drtlil.cc827 for (auto &it : selection_vars) in optimize()
4807 if (design->selection_vars.count(str) == 0) in parse_sel()
4811 RTLIL::Selection &sel = design->selection_vars.at(str); in parse_sel()
H A Drtlil.h1046 dict<RTLIL::IdString, RTLIL::Selection> selection_vars; member