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Searched refs:set_allow_signal_assignment (Results 1 – 2 of 2) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.hh795 void set_allow_signal_assignment(bool b) { sig_assign_ = b; } in set_allow_signal_assignment() function in vhdl_scope
H A Dscope.cc844 func->get_scope()->set_allow_signal_assignment(false); in draw_function()