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/dports/print/R-cran-knitr/knitr/
H A DNAMESPACE14 S3method(sew,character)
15 S3method(sew,default)
16 S3method(sew,error)
18 S3method(sew,knit_asis)
19 S3method(sew,knit_embed_url)
21 S3method(sew,list)
22 S3method(sew,message)
23 S3method(sew,recordedplot)
24 S3method(sew,source)
25 S3method(sew,warning)
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td1263 // cannot overlap the source vector register group
1283 // cannot overlap the source vector register group
1654 // * The destination EEW is smaller than the source EEW and the overlap is
1655 // in the lowest-numbered part of the source register group is legal.
1657 // * The destination EEW is greater than the source EEW, the source EMUL is
1705 // lowest-numbered part of the source register group."
1841 // The source EEW is 8, 16, 32, or 64.
1842 // When the destination EEW is different from source EEW, we need to use
1847 // lowest-numbered part of the source register group".
2357 // Same as above but source operands are swapped.
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td1196 // cannot overlap the source vector register group
1215 // cannot overlap the source vector register group
1585 // * The destination EEW is smaller than the source EEW and the overlap is
1586 // in the lowest-numbered part of the source register group is legal.
1588 // * The destination EEW is greater than the source EEW, the source EMUL is
1636 // lowest-numbered part of the source register group."
1763 // The source EEW is 8, 16, 32, or 64.
1764 // When the destination EEW is different from source EEW, we need to use
1769 // lowest-numbered part of the source register group".
2281 // Same as above but source operands are swapped.
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td1196 // cannot overlap the source vector register group
1215 // cannot overlap the source vector register group
1585 // * The destination EEW is smaller than the source EEW and the overlap is
1586 // in the lowest-numbered part of the source register group is legal.
1588 // * The destination EEW is greater than the source EEW, the source EMUL is
1636 // lowest-numbered part of the source register group."
1763 // The source EEW is 8, 16, 32, or 64.
1764 // When the destination EEW is different from source EEW, we need to use
1769 // lowest-numbered part of the source register group".
2281 // Same as above but source operands are swapped.
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td1196 // cannot overlap the source vector register group
1215 // cannot overlap the source vector register group
1585 // * The destination EEW is smaller than the source EEW and the overlap is
1586 // in the lowest-numbered part of the source register group is legal.
1588 // * The destination EEW is greater than the source EEW, the source EMUL is
1636 // lowest-numbered part of the source register group."
1763 // The source EEW is 8, 16, 32, or 64.
1764 // When the destination EEW is different from source EEW, we need to use
1769 // lowest-numbered part of the source register group".
2281 // Same as above but source operands are swapped.
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td1196 // cannot overlap the source vector register group
1215 // cannot overlap the source vector register group
1585 // * The destination EEW is smaller than the source EEW and the overlap is
1586 // in the lowest-numbered part of the source register group is legal.
1588 // * The destination EEW is greater than the source EEW, the source EMUL is
1636 // lowest-numbered part of the source register group."
1763 // The source EEW is 8, 16, 32, or 64.
1764 // When the destination EEW is different from source EEW, we need to use
1769 // lowest-numbered part of the source register group".
2281 // Same as above but source operands are swapped.
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td1196 // cannot overlap the source vector register group
1215 // cannot overlap the source vector register group
1585 // * The destination EEW is smaller than the source EEW and the overlap is
1586 // in the lowest-numbered part of the source register group is legal.
1588 // * The destination EEW is greater than the source EEW, the source EMUL is
1636 // lowest-numbered part of the source register group."
1763 // The source EEW is 8, 16, 32, or 64.
1764 // When the destination EEW is different from source EEW, we need to use
1769 // lowest-numbered part of the source register group".
2281 // Same as above but source operands are swapped.
[all …]
/dports/emulators/qemu5/qemu-5.2.0/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc124 * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
142 * The destination vector register group cannot overlap a source vector register
518 * groups cannot overlap the source vector register group (specified by
1312 * destination vector register overlaps a source vector register group.
1536 * if the destination vector register overlaps a source vector register group
1931 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1971 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2005 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2043 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2260 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc115 * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
133 * The destination vector register group cannot overlap a source vector register
498 * groups cannot overlap the source vector register group (specified by
1279 * destination vector register overlaps a source vector register group.
1501 * if the destination vector register overlaps a source vector register group
1891 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1932 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1966 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2005 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2222 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
[all …]
/dports/emulators/qemu/qemu-6.2.0/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc115 * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
133 * The destination vector register group cannot overlap a source vector register
498 * groups cannot overlap the source vector register group (specified by
1282 * destination vector register overlaps a source vector register group.
1504 * if the destination vector register overlaps a source vector register group
1895 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1936 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1970 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2009 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2226 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
[all …]
/dports/emulators/qemu60/qemu-6.0.0/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc124 * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
142 * The destination vector register group cannot overlap a source vector register
518 * groups cannot overlap the source vector register group (specified by
1312 * destination vector register overlaps a source vector register group.
1536 * if the destination vector register overlaps a source vector register group
1931 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
1971 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2005 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2043 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
2260 (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td487 // overlap the source mask register (v0), unless the destination vector register
1084 // cannot overlap the source vector register group
1104 // cannot overlap the source vector register group
1425 // * The destination EEW is smaller than the source EEW and the overlap is
1426 // in the lowest-numbered part of the source register group is legal.
1428 // * The destination EEW is greater than the source EEW, the source EMUL is
1596 // The source EEW is 8, 16, 32, or 64.
1597 // When the destination EEW is different from source EEW, we need to use
1598 // @earlyclobber to avoid the overlap between destination and source registers.
1971 int sew,
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td487 // overlap the source mask register (v0), unless the destination vector register
1084 // cannot overlap the source vector register group
1104 // cannot overlap the source vector register group
1425 // * The destination EEW is smaller than the source EEW and the overlap is
1426 // in the lowest-numbered part of the source register group is legal.
1428 // * The destination EEW is greater than the source EEW, the source EMUL is
1596 // The source EEW is 8, 16, 32, or 64.
1597 // When the destination EEW is different from source EEW, we need to use
1598 // @earlyclobber to avoid the overlap between destination and source registers.
1971 int sew,
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/testsuite/gas/mips/
H A Dmips16e-64.d4 #source: mips16e-64.s
12 0x00000000 ecd1 sew \$4
/dports/lang/gnatdroid-binutils/binutils-2.27/gas/testsuite/gas/mips/
H A Dmips16e-64.d4 #source: mips16e-64.s
12 0x00000000 ecd1 sew \$4
/dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/mips/
H A Dmips16e-64.d4 #source: mips16e-64.s
12 [0-9a-f]+ <[^>]*> ecd1 sew \$4
/dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/mips/
H A Dmips16e-64.d4 #source: mips16e-64.s
12 [0-9a-f]+ <[^>]*> ecd1 sew \$4
/dports/devel/binutils/binutils-2.37/gas/testsuite/gas/mips/
H A Dmips16e-64.d4 #source: mips16e-64.s
12 [0-9a-f]+ <[^>]*> ecd1 sew \$4
/dports/print/R-cran-knitr/knitr/man/
H A Dengine_output.Rd14 \item{code}{Source code of the chunk, to which the output hook \code{source}
23 A character string generated from the source code and output using
35 passed to \code{knitr::sew()} to return a character vector of final output.
46 out = list(structure(list(src = "1 + 1"), class = "source"),
/dports/lang/v8/v8-9.6.180.12/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.h586 void ExtractBits(Register dest, Register source, Register pos, int size,
588 sra(dest, source, pos);
593 void InsertBits(Register dest, Register source, Register pos, int size);
918 const Register& source);
931 VU.set(kScratchReg, sew, lmul); in WasmRvvExtractLane()
939 void WasmRvvEq(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
942 void WasmRvvNe(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
944 void WasmRvvGeS(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
946 void WasmRvvGeU(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
948 void WasmRvvGtS(VRegister dst, VRegister lhs, VRegister rhs, VSew sew,
[all …]
H A Dassembler-riscv64.h432 void sb(Register source, Register base, int16_t imm12);
433 void sh(Register source, Register base, int16_t imm12);
434 void sw(Register source, Register base, int16_t imm12);
483 void sd(Register source, Register base, int16_t imm12);
539 void fsw(FPURegister source, Register base, int16_t imm12);
581 void fsd(FPURegister source, Register base, int16_t imm12);
1211 sew_ = sew; in set()
1226 if (sew != sew_ || lmul != lmul_) { in set()
1227 sew_ = sew; in set()
1234 void set(VSew sew, Vlmul lmul) { in set() argument
[all …]
H A Dmacro-assembler-riscv64.cc3937 VSew sew, Vlmul lmul) { in WasmRvvEq() argument
3938 VU.set(kScratchReg, sew, lmul); in WasmRvvEq()
3946 VSew sew, Vlmul lmul) { in WasmRvvNe() argument
3947 VU.set(kScratchReg, sew, lmul); in WasmRvvNe()
3955 VSew sew, Vlmul lmul) { in WasmRvvGeS() argument
3956 VU.set(kScratchReg, sew, lmul); in WasmRvvGeS()
3964 VSew sew, Vlmul lmul) { in WasmRvvGeU() argument
3965 VU.set(kScratchReg, sew, lmul); in WasmRvvGeU()
3973 VSew sew, Vlmul lmul) { in WasmRvvGtS() argument
3974 VU.set(kScratchReg, sew, lmul); in WasmRvvGtS()
[all …]
/dports/security/py-gpgme/gpgme-1.15.1/lang/python/doc/src/
H A Dshort-history.org24 return to the source. This is a short explanation of that journey.
133 obtaining the GPGME source code would obtain the Python bindings
134 source code at the same time. Whereas there was the potential to
135 sew confusion amongst Python users installing the module from PyPI,
/dports/security/gpgme-cpp/gpgme-1.15.1/lang/python/doc/src/
H A Dshort-history.org24 return to the source. This is a short explanation of that journey.
133 obtaining the GPGME source code would obtain the Python bindings
134 source code at the same time. Whereas there was the potential to
135 sew confusion amongst Python users installing the module from PyPI,
/dports/security/gpgme-qt5/gpgme-1.15.1/lang/python/doc/src/
H A Dshort-history.org24 return to the source. This is a short explanation of that journey.
133 obtaining the GPGME source code would obtain the Python bindings
134 source code at the same time. Whereas there was the potential to
135 sew confusion amongst Python users installing the module from PyPI,

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