| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
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| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
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| H A D | exchange.ll | 14 %sext.a.0 = sext i16 %ld.a.0 to i32
18 %sext.a.1 = sext i16 %ld.a.1 to i32
19 %sext.b.1 = sext i16 %ld.b.1 to i32
20 %sext.b.0 = sext i16 %ld.b.0 to i32
21 %mul.0 = mul i32 %sext.a.0, %sext.b.1
22 %mul.1 = mul i32 %sext.a.1, %sext.b.0
39 %sext.a.0 = sext i16 %ld.a.0 to i32
43 %sext.a.1 = sext i16 %ld.a.1 to i32
44 %sext.b.1 = sext i16 %ld.b.1 to i32
45 %sext.b.0 = sext i16 %ld.b.0 to i32
[all …]
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| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
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| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
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| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
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| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
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| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
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| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/ARM/ParallelDSP/ |
| H A D | sext-acc.ll | 13 %sext.a.0 = sext i16 %ld.a.0 to i32
15 %sext.b.0 = sext i16 %ld.b.0 to i32
16 %mul.0 = mul i32 %sext.a.0, %sext.b.0
20 %sext.a.1 = sext i16 %ld.a.1 to i32
22 %sext.b.1 = sext i16 %ld.b.1 to i32
23 %mul.1 = mul i32 %sext.a.1, %sext.b.1
24 %sext.mul.0 = sext i32 %mul.0 to i64
25 %sext.mul.1 = sext i32 %mul.1 to i64
27 %sext.acc = sext i32 %acc to i64
47 %sext.a.0 = sext i16 %ld.a.0 to i32
[all …]
|
| H A D | blocks.ll | 12 %sext.a.0 = sext i16 %ld.a.0 to i32
14 %sext.b.0 = sext i16 %ld.b.0 to i32
15 %mul.0 = mul i32 %sext.a.0, %sext.b.0
19 %sext.a.1 = sext i16 %ld.a.1 to i32
21 %sext.b.1 = sext i16 %ld.b.1 to i32
22 %mul.1 = mul i32 %sext.a.1, %sext.b.1
37 %sext.a.0 = sext i16 %ld.a.0 to i32
39 %sext.b.0 = sext i16 %ld.b.0 to i32
44 %sext.a.1 = sext i16 %ld.a.1 to i32
46 %sext.b.1 = sext i16 %ld.b.1 to i32
[all …]
|