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/dports/devel/gdb/gdb-11.1/gdb/testsuite/gdb.reverse/
H A Dsolib-reverse.c34 shr1 (""); in main()
42 shr1 ("message 1\n"); /* shr1 one */ in main()
43 shr1 ("message 2\n"); /* shr1 two */ in main()
44 shr1 ("message 3\n"); /* shr1 three */ in main()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Hexagon/
H A Dcirc_ld.ll24 %shr1 = lshr i32 %conv, 1
28 %or = or i32 %shr1, 33554432
41 %shr1 = lshr i32 %conv, 1
46 %shl = shl nuw nsw i32 %shr1, 3
61 %shr1 = and i32 %conv, 65534
66 %or = or i32 %shr1, 50331648
80 %shr1 = lshr i32 %conv, 1
84 %or = or i32 %shr1, 33554432
97 %shr1 = and i32 %conv, 65534
102 %or = or i32 %shr1, 50331648
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3
/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/IndVarSimplify/
H A Dstrengthen-overflow.ll116 %shr1 = ashr i32 %shl, 1
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
137 %shr1 = ashr i32 %shl, 2
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
158 %shr1 = ashr i32 %shl, 2
159 ; CHECK: %shr1 = ashr exact i32 %shl, 2
179 %shr1 = ashr i32 %shl, 3
180 ; CHECK: %shr1 = ashr i32 %shl, 3

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