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Searched refs:sig_assign_ (Results 1 – 2 of 2) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.hh795 void set_allow_signal_assignment(bool b) { sig_assign_ = b; } in set_allow_signal_assignment()
796 bool allow_signal_assignment() const { return sig_assign_; } in allow_signal_assignment()
800 bool init_, sig_assign_; member in vhdl_scope
H A Dvhdl_syntax.cc34 : parent_(NULL), init_(false), sig_assign_(true), in vhdl_scope()