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Searched refs:simplify_subreg (Results 1 – 25 of 1017) sorted by relevance

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/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc9/gcc-9.4.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc48/gcc-4.8.5/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc11/gcc-11.2.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc10/gcc-10.3.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc8/gcc-8.5.0/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/ia64/
H A Dconstraints.md140 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
/dports/devel/avr-gcc/gcc-10.2.0/gcc/
H A Dsimplify-rtx.c257 rtx tem = simplify_subreg (GET_MODE (x), c, cmode, offset); in avoid_constant_pool_reference()
6802 simplify_subreg (machine_mode outermode, rtx op, in simplify_subreg() function
7000 res = simplify_subreg (outermode, part, part_mode, final_offset); in simplify_subreg()
7082 newx = simplify_subreg (outermode, op, innermode, byte); in simplify_gen_subreg()
7186 return simplify_subreg (mode, SUBREG_REG (x), in simplify_rtx()
7543 simplify_subreg (outer_mode, x,
7560 rtx outer_x = simplify_subreg (outer_mode, x, inner_mode, 0);
7562 ASSERT_RTX_EQ (x, simplify_subreg (inner_mode, outer_x,
7588 simplify_subreg (QImode, x, inner_mode, byte));
7729 ASSERT_EQ (simplify_subreg (HImode, x5, QImode, 0), x8);
[all …]
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/
H A Dsimplify-rtx.c257 rtx tem = simplify_subreg (GET_MODE (x), c, cmode, offset); in avoid_constant_pool_reference()
6802 simplify_subreg (machine_mode outermode, rtx op, in simplify_subreg() function
7000 res = simplify_subreg (outermode, part, part_mode, final_offset); in simplify_subreg()
7082 newx = simplify_subreg (outermode, op, innermode, byte); in simplify_gen_subreg()
7186 return simplify_subreg (mode, SUBREG_REG (x), in simplify_rtx()
7543 simplify_subreg (outer_mode, x,
7560 rtx outer_x = simplify_subreg (outer_mode, x, inner_mode, 0);
7562 ASSERT_RTX_EQ (x, simplify_subreg (inner_mode, outer_x,
7588 simplify_subreg (QImode, x, inner_mode, byte));
7729 ASSERT_EQ (simplify_subreg (HImode, x5, QImode, 0), x8);
[all …]
/dports/lang/gcc10/gcc-10.3.0/gcc/
H A Dsimplify-rtx.c257 rtx tem = simplify_subreg (GET_MODE (x), c, cmode, offset); in avoid_constant_pool_reference()
6802 simplify_subreg (machine_mode outermode, rtx op, in simplify_subreg() function
7000 res = simplify_subreg (outermode, part, part_mode, final_offset); in simplify_subreg()
7082 newx = simplify_subreg (outermode, op, innermode, byte); in simplify_gen_subreg()
7186 return simplify_subreg (mode, SUBREG_REG (x), in simplify_rtx()
7543 simplify_subreg (outer_mode, x,
7560 rtx outer_x = simplify_subreg (outer_mode, x, inner_mode, 0);
7562 ASSERT_RTX_EQ (x, simplify_subreg (inner_mode, outer_x,
7588 simplify_subreg (QImode, x, inner_mode, byte));
7729 ASSERT_EQ (simplify_subreg (HImode, x5, QImode, 0), x8);
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/gcc/
H A Dsimplify-rtx.c153 c = simplify_subreg (GET_MODE (x), c, cmode, 0); in avoid_constant_pool_reference()
3256 simplify_subreg (enum machine_mode outermode, rtx op, in simplify_subreg() function
3343 new = simplify_subreg (outermode, SUBREG_REG (op), in simplify_subreg()
3424 res = simplify_subreg (outermode, part, GET_MODE (part), final_offset); in simplify_subreg()
3457 new = simplify_subreg (outermode, op, innermode, byte); in simplify_gen_subreg()

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