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/dports/cad/yosys/yosys-yosys-0.12/passes/techmap/
H A Dclkbufmap.cc160 pool<SigBit> sink_wire_bits; in execute() local
172 sink_wire_bits.insert(sigmap(port.second[i])); in execute()
192 if (it != inv_ports_out.end() && !buf_wire_bits.count(bit) && sink_wire_bits.count(bit)) { in execute()
195 sink_wire_bits.insert(other_bit); in execute()
250 } else if (!sink_wire_bits.count(mapped_wire_bit)) { in execute()