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Searched refs:slice_width_ (Results 1 – 2 of 2) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.cc585 slice_width_ = w; in set_slice()
611 if (slice_width_ > 0) { in emit()
613 of << " + " << slice_width_ << " downto "; in emit()
H A Dvhdl_syntax.hh75 : vhdl_expr(type), name_(name), slice_(slice), slice_width_(0) {} in vhdl_var_ref()
86 unsigned slice_width_; member in vhdl_var_ref