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/dports/emulators/qemu42/qemu-4.2.1/hw/isa/
H A Dvt82c686.c168 uint32_t smb_io_base; member
368 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); in vt82c686b_pm_realize()
369 pci_conf[0x90] = s->smb_io_base | 1; in vt82c686b_pm_realize()
370 pci_conf[0x91] = s->smb_io_base >> 8; in vt82c686b_pm_realize()
373 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); in vt82c686b_pm_realize()
386 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in vt82c686b_pm_init() argument
393 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); in vt82c686b_pm_init()
403 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
/dports/emulators/qemu-utils/qemu-4.2.1/hw/isa/
H A Dvt82c686.c168 uint32_t smb_io_base; member
368 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); in vt82c686b_pm_realize()
369 pci_conf[0x90] = s->smb_io_base | 1; in vt82c686b_pm_realize()
370 pci_conf[0x91] = s->smb_io_base >> 8; in vt82c686b_pm_realize()
373 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); in vt82c686b_pm_realize()
386 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in vt82c686b_pm_init() argument
393 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); in vt82c686b_pm_init()
403 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/isa/
H A Dvt82c686.c169 uint32_t smb_io_base; member
369 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); in vt82c686b_pm_realize()
370 pci_conf[0x90] = s->smb_io_base | 1; in vt82c686b_pm_realize()
371 pci_conf[0x91] = s->smb_io_base >> 8; in vt82c686b_pm_realize()
374 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); in vt82c686b_pm_realize()
387 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in vt82c686b_pm_init() argument
394 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); in vt82c686b_pm_init()
404 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
/dports/emulators/qemu5/qemu-5.2.0/hw/isa/
H A Dvt82c686.c168 uint32_t smb_io_base; member
365 s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0); in vt82c686b_pm_realize()
366 pci_conf[0x90] = s->smb_io_base | 1; in vt82c686b_pm_realize()
367 pci_conf[0x91] = s->smb_io_base >> 8; in vt82c686b_pm_realize()
370 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); in vt82c686b_pm_realize()
383 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in vt82c686b_pm_init() argument
390 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); in vt82c686b_pm_init()
400 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/isa/
H A Dvt82c686.c167 uint32_t smb_io_base;
367 s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0);
368 pci_conf[0x90] = s->smb_io_base | 1;
369 pci_conf[0x91] = s->smb_io_base >> 8;
372 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
385 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
392 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
402 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/isa/
H A Dvt82c686.c167 uint32_t smb_io_base; member
367 s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0); in vt82c686b_pm_realize()
368 pci_conf[0x90] = s->smb_io_base | 1; in vt82c686b_pm_realize()
369 pci_conf[0x91] = s->smb_io_base >> 8; in vt82c686b_pm_realize()
372 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); in vt82c686b_pm_realize()
385 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in vt82c686b_pm_init() argument
392 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); in vt82c686b_pm_init()
402 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
/dports/emulators/qemu42/qemu-4.2.1/hw/acpi/
H A Dpiix4.c70 uint32_t smb_io_base; member
142 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); in smbus_io_space_update()
143 s->smb_io_base &= 0xffc0; in smbus_io_space_update()
147 memory_region_set_address(&s->smb.io, s->smb_io_base); in smbus_io_space_update()
481 pci_conf[0x90] = s->smb_io_base | 1; in piix4_pm_realize()
482 pci_conf[0x91] = s->smb_io_base >> 8; in piix4_pm_realize()
487 s->smb_io_base, &s->smb.io); in piix4_pm_realize()
512 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in piix4_pm_init() argument
520 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); in piix4_pm_init()
629 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu/qemu-6.2.0/hw/acpi/
H A Dpiix4.c73 uint32_t smb_io_base; member
146 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); in smbus_io_space_update()
147 s->smb_io_base &= 0xffc0; in smbus_io_space_update()
151 memory_region_set_address(&s->smb.io, s->smb_io_base); in smbus_io_space_update()
494 pci_conf[0x90] = s->smb_io_base | 1; in piix4_pm_realize()
495 pci_conf[0x91] = s->smb_io_base >> 8; in piix4_pm_realize()
500 s->smb_io_base, &s->smb.io); in piix4_pm_realize()
526 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in piix4_pm_init() argument
536 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); in piix4_pm_init()
646 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu60/qemu-6.0.0/hw/acpi/
H A Dpiix4.c72 uint32_t smb_io_base; member
145 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); in smbus_io_space_update()
146 s->smb_io_base &= 0xffc0; in smbus_io_space_update()
150 memory_region_set_address(&s->smb.io, s->smb_io_base); in smbus_io_space_update()
493 pci_conf[0x90] = s->smb_io_base | 1; in piix4_pm_realize()
494 pci_conf[0x91] = s->smb_io_base >> 8; in piix4_pm_realize()
499 s->smb_io_base, &s->smb.io); in piix4_pm_realize()
525 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in piix4_pm_init() argument
535 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); in piix4_pm_init()
645 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu5/qemu-5.2.0/hw/acpi/
H A Dpiix4.c72 uint32_t smb_io_base; member
144 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); in smbus_io_space_update()
145 s->smb_io_base &= 0xffc0; in smbus_io_space_update()
149 memory_region_set_address(&s->smb.io, s->smb_io_base); in smbus_io_space_update()
484 pci_conf[0x90] = s->smb_io_base | 1; in piix4_pm_realize()
485 pci_conf[0x91] = s->smb_io_base >> 8; in piix4_pm_realize()
490 s->smb_io_base, &s->smb.io); in piix4_pm_realize()
515 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in piix4_pm_init() argument
525 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); in piix4_pm_init()
635 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu-utils/qemu-4.2.1/hw/acpi/
H A Dpiix4.c70 uint32_t smb_io_base; member
142 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); in smbus_io_space_update()
143 s->smb_io_base &= 0xffc0; in smbus_io_space_update()
147 memory_region_set_address(&s->smb.io, s->smb_io_base); in smbus_io_space_update()
481 pci_conf[0x90] = s->smb_io_base | 1; in piix4_pm_realize()
482 pci_conf[0x91] = s->smb_io_base >> 8; in piix4_pm_realize()
487 s->smb_io_base, &s->smb.io); in piix4_pm_realize()
512 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in piix4_pm_init() argument
520 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); in piix4_pm_init()
629 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/acpi/
H A Dpiix4.c74 uint32_t smb_io_base; member
148 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); in smbus_io_space_update()
149 s->smb_io_base &= 0xffc0; in smbus_io_space_update()
153 memory_region_set_address(&s->smb.io, s->smb_io_base); in smbus_io_space_update()
512 pci_conf[0x90] = s->smb_io_base | 1; in piix4_pm_realize()
513 pci_conf[0x91] = s->smb_io_base >> 8; in piix4_pm_realize()
518 s->smb_io_base, &s->smb.io); in piix4_pm_realize()
554 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in piix4_pm_init() argument
562 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); in piix4_pm_init()
672 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/acpi/
H A Dpiix4.c71 uint32_t smb_io_base; member
143 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); in smbus_io_space_update()
144 s->smb_io_base &= 0xffc0; in smbus_io_space_update()
148 memory_region_set_address(&s->smb.io, s->smb_io_base); in smbus_io_space_update()
482 pci_conf[0x90] = s->smb_io_base | 1; in piix4_pm_realize()
483 pci_conf[0x91] = s->smb_io_base >> 8; in piix4_pm_realize()
488 s->smb_io_base, &s->smb.io); in piix4_pm_realize()
513 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in piix4_pm_init() argument
521 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); in piix4_pm_init()
630 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/acpi/
H A Dpiix4.c71 uint32_t smb_io_base;
143 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
144 s->smb_io_base &= 0xffc0;
148 memory_region_set_address(&s->smb.io, s->smb_io_base);
482 pci_conf[0x90] = s->smb_io_base | 1;
483 pci_conf[0x91] = s->smb_io_base >> 8;
488 s->smb_io_base, &s->smb.io);
513 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
521 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
630 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/acpi/
H A Dpiix4.c73 uint32_t smb_io_base; member
146 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90)); in smbus_io_space_update()
147 s->smb_io_base &= 0xffc0; in smbus_io_space_update()
151 memory_region_set_address(&s->smb.io, s->smb_io_base); in smbus_io_space_update()
494 pci_conf[0x90] = s->smb_io_base | 1; in piix4_pm_realize()
495 pci_conf[0x91] = s->smb_io_base >> 8; in piix4_pm_realize()
500 s->smb_io_base, &s->smb.io); in piix4_pm_realize()
526 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, in piix4_pm_init() argument
536 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base); in piix4_pm_init()
646 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
/dports/emulators/qemu42/qemu-4.2.1/include/hw/isa/
H A Dvt82c686.h11 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/isa/
H A Dvt82c686.h11 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/isa/
H A Dvt82c686.h10 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu5/qemu-5.2.0/include/hw/isa/
H A Dvt82c686.h11 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/isa/
H A Dvt82c686.h11 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/isa/
H A Dvt82c686.h11 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/southbridge/
H A Dpiix.h19 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/southbridge/
H A Dpiix.h19 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu42/qemu-4.2.1/include/hw/southbridge/
H A Dpiix.h19 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/southbridge/
H A Dpiix.h19 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,

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