/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/RISCV/ |
H A D | umulo-128-legalisation-lowering.ll | 65 ; RISCV32-NEXT: snez a4, s3 66 ; RISCV32-NEXT: snez s1, a0 68 ; RISCV32-NEXT: snez s1, s4 69 ; RISCV32-NEXT: snez s0, a2 72 ; RISCV32-NEXT: snez s0, s0 75 ; RISCV32-NEXT: snez s0, s0 79 ; RISCV32-NEXT: snez s0, s0 83 ; RISCV32-NEXT: snez a4, a4 95 ; RISCV32-NEXT: snez a1, a1 96 ; RISCV32-NEXT: snez a0, a0
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H A D | setcc-logic.ll | 37 ; RV32I-NEXT: snez a0, a0 47 ; RV64I-NEXT: snez a0, a0 84 ; RV32I-NEXT: snez a0, a0 94 ; RV64I-NEXT: snez a0, a0 106 ; RV32I-NEXT: snez a1, a1 108 ; RV32I-NEXT: snez a0, a0 117 ; RV64I-NEXT: snez a1, a1 119 ; RV64I-NEXT: snez a0, a0
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/RISCV/ |
H A D | setcc-logic.ll | 36 ; RV32I-NEXT: snez a0, a0 45 ; RV64I-NEXT: snez a0, a0 82 ; RV32I-NEXT: snez a0, a0 89 ; RV64I-NEXT: snez a0, a0 101 ; RV32I-NEXT: snez a1, a1 103 ; RV32I-NEXT: snez a0, a0 111 ; RV64I-NEXT: snez a1, a1 113 ; RV64I-NEXT: snez a0, a0
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H A D | umulo-128-legalisation-lowering.ll | 67 ; RISCV32-NEXT: snez s0, a3 68 ; RISCV32-NEXT: snez s1, a7 71 ; RISCV32-NEXT: snez s1, s1 74 ; RISCV32-NEXT: snez a3, a3 78 ; RISCV32-NEXT: snez s1, a2 79 ; RISCV32-NEXT: snez s0, a6 82 ; RISCV32-NEXT: snez s0, s0 85 ; RISCV32-NEXT: snez a2, a2 89 ; RISCV32-NEXT: snez a3, a3 91 ; RISCV32-NEXT: snez s1, s1
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/ |
H A D | setcc-logic.ll | 36 ; RV32I-NEXT: snez a0, a0 45 ; RV64I-NEXT: snez a0, a0 82 ; RV32I-NEXT: snez a0, a0 90 ; RV64I-NEXT: snez a0, a0 102 ; RV32I-NEXT: snez a1, a1 104 ; RV32I-NEXT: snez a0, a0 112 ; RV64I-NEXT: snez a1, a1 114 ; RV64I-NEXT: snez a0, a0
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H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/ |
H A D | setcc-logic.ll | 36 ; RV32I-NEXT: snez a0, a0 45 ; RV64I-NEXT: snez a0, a0 82 ; RV32I-NEXT: snez a0, a0 90 ; RV64I-NEXT: snez a0, a0 102 ; RV32I-NEXT: snez a1, a1 104 ; RV32I-NEXT: snez a0, a0 112 ; RV64I-NEXT: snez a1, a1 114 ; RV64I-NEXT: snez a0, a0
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H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/ |
H A D | setcc-logic.ll | 36 ; RV32I-NEXT: snez a0, a0 45 ; RV64I-NEXT: snez a0, a0 82 ; RV32I-NEXT: snez a0, a0 90 ; RV64I-NEXT: snez a0, a0 102 ; RV32I-NEXT: snez a1, a1 104 ; RV32I-NEXT: snez a0, a0 112 ; RV64I-NEXT: snez a1, a1 114 ; RV64I-NEXT: snez a0, a0
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H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/ |
H A D | setcc-logic.ll | 36 ; RV32I-NEXT: snez a0, a0 45 ; RV64I-NEXT: snez a0, a0 82 ; RV32I-NEXT: snez a0, a0 90 ; RV64I-NEXT: snez a0, a0 102 ; RV32I-NEXT: snez a1, a1 104 ; RV32I-NEXT: snez a0, a0 112 ; RV64I-NEXT: snez a1, a1 114 ; RV64I-NEXT: snez a0, a0
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H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/ |
H A D | setcc-logic.ll | 36 ; RV32I-NEXT: snez a0, a0 45 ; RV64I-NEXT: snez a0, a0 82 ; RV32I-NEXT: snez a0, a0 90 ; RV64I-NEXT: snez a0, a0 102 ; RV32I-NEXT: snez a1, a1 104 ; RV32I-NEXT: snez a0, a0 112 ; RV64I-NEXT: snez a1, a1 114 ; RV64I-NEXT: snez a0, a0
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/RISCV/ |
H A D | setcc-logic.ll | 36 ; RV32I-NEXT: snez a0, a0 45 ; RV64I-NEXT: snez a0, a0 82 ; RV32I-NEXT: snez a0, a0 90 ; RV64I-NEXT: snez a0, a0 102 ; RV32I-NEXT: snez a1, a1 104 ; RV32I-NEXT: snez a0, a0 112 ; RV64I-NEXT: snez a1, a1 114 ; RV64I-NEXT: snez a0, a0
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/RISCV/ |
H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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H A D | setcc-logic.ll | 37 ; RV32I-NEXT: snez a0, a0 47 ; RV64I-NEXT: snez a0, a0 84 ; RV32I-NEXT: snez a0, a0 94 ; RV64I-NEXT: snez a0, a0 106 ; RV32I-NEXT: snez a1, a1 108 ; RV32I-NEXT: snez a0, a0 117 ; RV64I-NEXT: snez a1, a1 119 ; RV64I-NEXT: snez a0, a0
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/RISCV/ |
H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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H A D | setcc-logic.ll | 37 ; RV32I-NEXT: snez a0, a0 47 ; RV64I-NEXT: snez a0, a0 84 ; RV32I-NEXT: snez a0, a0 94 ; RV64I-NEXT: snez a0, a0 106 ; RV32I-NEXT: snez a1, a1 108 ; RV32I-NEXT: snez a0, a0 117 ; RV64I-NEXT: snez a1, a1 119 ; RV64I-NEXT: snez a0, a0
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/RISCV/ |
H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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H A D | setcc-logic.ll | 37 ; RV32I-NEXT: snez a0, a0 47 ; RV64I-NEXT: snez a0, a0 84 ; RV32I-NEXT: snez a0, a0 94 ; RV64I-NEXT: snez a0, a0 106 ; RV32I-NEXT: snez a1, a1 108 ; RV32I-NEXT: snez a0, a0 117 ; RV64I-NEXT: snez a1, a1 119 ; RV64I-NEXT: snez a0, a0
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/RISCV/ |
H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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H A D | setcc-logic.ll | 37 ; RV32I-NEXT: snez a0, a0 47 ; RV64I-NEXT: snez a0, a0 84 ; RV32I-NEXT: snez a0, a0 94 ; RV64I-NEXT: snez a0, a0 106 ; RV32I-NEXT: snez a1, a1 108 ; RV32I-NEXT: snez a0, a0 117 ; RV64I-NEXT: snez a1, a1 119 ; RV64I-NEXT: snez a0, a0
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/RISCV/ |
H A D | umulo-128-legalisation-lowering.ll | 66 ; RISCV32-NEXT: snez a1, s8 67 ; RISCV32-NEXT: snez a3, s3 70 ; RISCV32-NEXT: snez a3, a3 73 ; RISCV32-NEXT: snez a3, a3 77 ; RISCV32-NEXT: snez a3, s5 78 ; RISCV32-NEXT: snez a4, s2 81 ; RISCV32-NEXT: snez a4, a4 84 ; RISCV32-NEXT: snez a4, a4 88 ; RISCV32-NEXT: snez a3, a3 90 ; RISCV32-NEXT: snez a4, a4
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H A D | setcc-logic.ll | 37 ; RV32I-NEXT: snez a0, a0 47 ; RV64I-NEXT: snez a0, a0 84 ; RV32I-NEXT: snez a0, a0 94 ; RV64I-NEXT: snez a0, a0 106 ; RV32I-NEXT: snez a1, a1 108 ; RV32I-NEXT: snez a0, a0 117 ; RV64I-NEXT: snez a1, a1 119 ; RV64I-NEXT: snez a0, a0
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/RISCV/ |
H A D | umulo-128-legalisation-lowering.ll | 74 ; RISCV32-NEXT: snez a0, s5 75 ; RISCV32-NEXT: snez a2, t2 77 ; RISCV32-NEXT: snez a2, s6 78 ; RISCV32-NEXT: snez a5, t3 81 ; RISCV32-NEXT: snez a5, a5 84 ; RISCV32-NEXT: snez a5, a5 88 ; RISCV32-NEXT: snez s1, s1 92 ; RISCV32-NEXT: snez a5, a5 104 ; RISCV32-NEXT: snez a3, a3 105 ; RISCV32-NEXT: snez a1, a1
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