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Searched refs:spisr (Results 1 – 25 of 67) sorted by relevance

123

/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/spi/
H A Dxilinx_spi.c94 u32 spisr; /* SPI Status Register (SPISR) */ member
175 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) && in xilinx_spi_fill_txfifo()
195 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) { in xilinx_spi_read_rxfifo()
289 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true, in xilinx_spi_xfer()

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