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Searched refs:sust (Results 1 – 25 of 186) sorted by relevance

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/dports/audio/gnuitar/gnuitar-0.3.2/src/
H A Dsustain.c75 params->sust = (int) adj->value * 2.56; in update_sustain_sust()
116 GtkWidget *sust; in sustain_init() local
167 gtk_adjustment_new(psustain->sust / 2.56, 0.0, 101.0, 1.0, 1.0, in sustain_init()
179 sust = gtk_vscale_new(GTK_ADJUSTMENT(adj_sust)); in sustain_init()
181 gtk_table_attach(GTK_TABLE(parmTable), sust, 3, 4, 1, 2, in sustain_init()
248 CompW1 = ds->sust / 100.0f; in sustain_filter()
295 write(fd, &sp->sust, sizeof(sp->sust)); in sustain_save()
307 read(fd, &sp->sust, sizeof(sp->sust)); in sustain_load()
348 psustain->sust = 256; in sustain_create()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/NVPTX/
H A Dsurf-write-cuda.ll6 declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32)
14 ; SM20: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
16 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
17 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val)
31 ; SM20: sust.b.1d.b32.trap [surf0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
32 ; SM30: sust.b.1d.b32.trap [%rd[[SURFREG]], {%r{{[0-9]+}}}], {%r{{[0-9]+}}}
33 tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %surfHandle, i32 %idx, i32 %val)
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td2874 "llvm.nvvm.sust.b.1d.i8.clamp">,
2976 "llvm.nvvm.sust.b.2d.i8.clamp">,
3144 "llvm.nvvm.sust.b.1d.i8.trap">,
3246 "llvm.nvvm.sust.b.2d.i8.trap">,
3357 "llvm.nvvm.sust.b.3d.i8.trap">,
3414 "llvm.nvvm.sust.b.1d.i8.zero">,
3516 "llvm.nvvm.sust.b.2d.i8.zero">,
3627 "llvm.nvvm.sust.b.3d.i8.zero">,
3686 "llvm.nvvm.sust.p.1d.i8.trap">,
3771 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]
/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/include/llvm/IR/
H A DIntrinsicsNVVM.td2602 "llvm.nvvm.sust.b.1d.i8.clamp">,
2704 "llvm.nvvm.sust.b.2d.i8.clamp">,
2872 "llvm.nvvm.sust.b.1d.i8.trap">,
2974 "llvm.nvvm.sust.b.2d.i8.trap">,
3085 "llvm.nvvm.sust.b.3d.i8.trap">,
3142 "llvm.nvvm.sust.b.1d.i8.zero">,
3244 "llvm.nvvm.sust.b.2d.i8.zero">,
3355 "llvm.nvvm.sust.b.3d.i8.zero">,
3414 "llvm.nvvm.sust.p.1d.i8.trap">,
3499 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td2881 "llvm.nvvm.sust.b.1d.i8.clamp">,
2983 "llvm.nvvm.sust.b.2d.i8.clamp">,
3151 "llvm.nvvm.sust.b.1d.i8.trap">,
3253 "llvm.nvvm.sust.b.2d.i8.trap">,
3364 "llvm.nvvm.sust.b.3d.i8.trap">,
3421 "llvm.nvvm.sust.b.1d.i8.zero">,
3523 "llvm.nvvm.sust.b.2d.i8.zero">,
3634 "llvm.nvvm.sust.b.3d.i8.zero">,
3693 "llvm.nvvm.sust.p.1d.i8.trap">,
3778 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/include/llvm/IR/
H A DIntrinsicsNVVM.td2881 "llvm.nvvm.sust.b.1d.i8.clamp">,
2983 "llvm.nvvm.sust.b.2d.i8.clamp">,
3151 "llvm.nvvm.sust.b.1d.i8.trap">,
3253 "llvm.nvvm.sust.b.2d.i8.trap">,
3364 "llvm.nvvm.sust.b.3d.i8.trap">,
3421 "llvm.nvvm.sust.b.1d.i8.zero">,
3523 "llvm.nvvm.sust.b.2d.i8.zero">,
3634 "llvm.nvvm.sust.b.3d.i8.zero">,
3693 "llvm.nvvm.sust.p.1d.i8.trap">,
3778 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]
/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/include/llvm/IR/
H A DIntrinsicsNVVM.td2602 "llvm.nvvm.sust.b.1d.i8.clamp">,
2704 "llvm.nvvm.sust.b.2d.i8.clamp">,
2872 "llvm.nvvm.sust.b.1d.i8.trap">,
2974 "llvm.nvvm.sust.b.2d.i8.trap">,
3085 "llvm.nvvm.sust.b.3d.i8.trap">,
3142 "llvm.nvvm.sust.b.1d.i8.zero">,
3244 "llvm.nvvm.sust.b.2d.i8.zero">,
3355 "llvm.nvvm.sust.b.3d.i8.zero">,
3414 "llvm.nvvm.sust.p.1d.i8.trap">,
3499 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]
/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/include/llvm/IR/
H A DIntrinsicsNVVM.td2602 "llvm.nvvm.sust.b.1d.i8.clamp">,
2704 "llvm.nvvm.sust.b.2d.i8.clamp">,
2872 "llvm.nvvm.sust.b.1d.i8.trap">,
2974 "llvm.nvvm.sust.b.2d.i8.trap">,
3085 "llvm.nvvm.sust.b.3d.i8.trap">,
3142 "llvm.nvvm.sust.b.1d.i8.zero">,
3244 "llvm.nvvm.sust.b.2d.i8.zero">,
3355 "llvm.nvvm.sust.b.3d.i8.zero">,
3414 "llvm.nvvm.sust.p.1d.i8.trap">,
3499 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td2874 "llvm.nvvm.sust.b.1d.i8.clamp">,
2976 "llvm.nvvm.sust.b.2d.i8.clamp">,
3144 "llvm.nvvm.sust.b.1d.i8.trap">,
3246 "llvm.nvvm.sust.b.2d.i8.trap">,
3357 "llvm.nvvm.sust.b.3d.i8.trap">,
3414 "llvm.nvvm.sust.b.1d.i8.zero">,
3516 "llvm.nvvm.sust.b.2d.i8.zero">,
3627 "llvm.nvvm.sust.b.3d.i8.zero">,
3686 "llvm.nvvm.sust.p.1d.i8.trap">,
3771 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/include/llvm/IR/
H A DIntrinsicsNVVM.td2881 "llvm.nvvm.sust.b.1d.i8.clamp">,
2983 "llvm.nvvm.sust.b.2d.i8.clamp">,
3151 "llvm.nvvm.sust.b.1d.i8.trap">,
3253 "llvm.nvvm.sust.b.2d.i8.trap">,
3364 "llvm.nvvm.sust.b.3d.i8.trap">,
3421 "llvm.nvvm.sust.b.1d.i8.zero">,
3523 "llvm.nvvm.sust.b.2d.i8.zero">,
3634 "llvm.nvvm.sust.b.3d.i8.zero">,
3693 "llvm.nvvm.sust.p.1d.i8.trap">,
3778 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td2881 "llvm.nvvm.sust.b.1d.i8.clamp">,
2983 "llvm.nvvm.sust.b.2d.i8.clamp">,
3151 "llvm.nvvm.sust.b.1d.i8.trap">,
3253 "llvm.nvvm.sust.b.2d.i8.trap">,
3364 "llvm.nvvm.sust.b.3d.i8.trap">,
3421 "llvm.nvvm.sust.b.1d.i8.zero">,
3523 "llvm.nvvm.sust.b.2d.i8.zero">,
3634 "llvm.nvvm.sust.b.3d.i8.zero">,
3693 "llvm.nvvm.sust.p.1d.i8.trap">,
3778 "llvm.nvvm.sust.p.2d.i8.trap">,
[all …]

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