Home
last modified time | relevance | path

Searched refs:tcg_const_reg (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu-utils/qemu-4.2.1/target/hppa/
H A Dtranslate.c146 #define tcg_const_reg tcg_const_i64 macro
240 #define tcg_const_reg tcg_const_i32 macro
488 cond->a1 = tcg_const_reg(0); in cond_prep()
794 tmp = tcg_const_reg(ctx->insn); in gen_excp_iir()
1157 TCGv_reg zero = tcg_const_reg(0); in do_add()
1249 zero = tcg_const_reg(0); in do_sub()
2612 ci = tcg_const_reg(0); in trans_lci()
2838 zero = tcg_const_reg(0); in trans_ds()
2961 zero = tcg_const_reg(0); in trans_ldc()
3414 mask = tcg_const_reg(msb + (msb - 1)); in do_depw_sar()
/dports/emulators/qemu5/qemu-5.2.0/target/hppa/
H A Dtranslate.c146 #define tcg_const_reg tcg_const_i64 macro
240 #define tcg_const_reg tcg_const_i32 macro
488 cond->a1 = tcg_const_reg(0); in cond_prep()
794 tmp = tcg_const_reg(ctx->insn); in gen_excp_iir()
1157 TCGv_reg zero = tcg_const_reg(0); in do_add()
1249 zero = tcg_const_reg(0); in do_sub()
2614 ci = tcg_const_reg(0); in trans_lci()
2840 zero = tcg_const_reg(0); in trans_ds()
2974 zero = tcg_const_reg(0); in trans_ldc()
3429 mask = tcg_const_reg(msb + (msb - 1)); in do_depw_sar()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/hppa/
H A Dtranslate.c146 #define tcg_const_reg tcg_const_i64 macro
240 #define tcg_const_reg tcg_const_i32 macro
488 cond->a1 = tcg_const_reg(0); in cond_prep()
794 tmp = tcg_const_reg(ctx->insn); in gen_excp_iir()
1157 TCGv_reg zero = tcg_const_reg(0); in do_add()
1249 zero = tcg_const_reg(0); in do_sub()
2614 ci = tcg_const_reg(0); in trans_lci()
2840 zero = tcg_const_reg(0); in trans_ds()
2974 zero = tcg_const_reg(0); in trans_ldc()
3429 mask = tcg_const_reg(msb + (msb - 1)); in do_depw_sar()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/hppa/
H A Dtranslate.c146 #define tcg_const_reg tcg_const_i64 macro
240 #define tcg_const_reg tcg_const_i32 macro
435 cond->a1 = tcg_const_reg(0); in cond_prep()
736 TCGv_reg tmp = tcg_const_reg(ctx->insn); in gen_excp_iir()
1141 TCGv_reg zero = tcg_const_reg(0); in do_add()
1206 zero = tcg_const_reg(0); in do_sub()
2510 ci = tcg_const_reg(0); in trans_lci()
2777 zero = tcg_const_reg(0); in trans_ds()
3026 zero = tcg_const_reg(0); in trans_ldcw()
3749 mask = tcg_const_reg(msb + (msb - 1)); in trans_depw_sar()
/dports/emulators/qemu42/qemu-4.2.1/target/hppa/
H A Dtranslate.c146 #define tcg_const_reg tcg_const_i64 macro
240 #define tcg_const_reg tcg_const_i32 macro
488 cond->a1 = tcg_const_reg(0); in cond_prep()
794 tmp = tcg_const_reg(ctx->insn); in gen_excp_iir()
1157 TCGv_reg zero = tcg_const_reg(0); in do_add()
1249 zero = tcg_const_reg(0); in do_sub()
2612 ci = tcg_const_reg(0); in trans_lci()
2838 zero = tcg_const_reg(0); in trans_ds()
2961 zero = tcg_const_reg(0); in trans_ldc()
3414 mask = tcg_const_reg(msb + (msb - 1)); in do_depw_sar()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/hppa/
H A Dtranslate.c146 #define tcg_const_reg tcg_const_i64 macro
240 #define tcg_const_reg tcg_const_i32 macro
488 cond->a1 = tcg_const_reg(0); in cond_prep()
794 tmp = tcg_const_reg(ctx->insn); in gen_excp_iir()
1157 TCGv_reg zero = tcg_const_reg(0); in do_add()
1249 zero = tcg_const_reg(0); in do_sub()
2612 ci = tcg_const_reg(0); in trans_lci()
2838 zero = tcg_const_reg(0); in trans_ds()
2972 zero = tcg_const_reg(0); in trans_ldc()
3427 mask = tcg_const_reg(msb + (msb - 1)); in do_depw_sar()
/dports/emulators/qemu60/qemu-6.0.0/target/hppa/
H A Dtranslate.c146 #define tcg_const_reg tcg_const_i64 macro
240 #define tcg_const_reg tcg_const_i32 macro
488 cond->a1 = tcg_const_reg(0); in cond_prep()
794 tmp = tcg_const_reg(ctx->insn); in gen_excp_iir()
1157 TCGv_reg zero = tcg_const_reg(0); in do_add()
1249 zero = tcg_const_reg(0); in do_sub()
2614 ci = tcg_const_reg(0); in trans_lci()
2840 zero = tcg_const_reg(0); in trans_ds()
2974 zero = tcg_const_reg(0); in trans_ldc()
3429 mask = tcg_const_reg(msb + (msb - 1)); in do_depw_sar()
/dports/emulators/qemu/qemu-6.2.0/target/hppa/
H A Dtranslate.c143 #define tcg_const_reg tcg_const_i64 macro
237 #define tcg_const_reg tcg_const_i32 macro
3373 mask = tcg_const_reg(msb + (msb - 1)); in do_depw_sar()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/hppa/
H A Dtranslate.c143 #define tcg_const_reg tcg_const_i64 macro
237 #define tcg_const_reg tcg_const_i32 macro
3381 mask = tcg_const_reg(msb + (msb - 1)); in do_depw_sar()