| /dports/emulators/qemu/qemu-6.2.0/target/hppa/ |
| H A D | translate.c | 124 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
218 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1013 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1031 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1040 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1083 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2629 return do_log_reg(ctx, a, tcg_gen_andc_reg); in trans_andcm()
3378 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in do_depw_sar()
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| /dports/emulators/qemu-utils/qemu-4.2.1/target/hppa/ |
| H A D | translate.c | 127 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
221 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1047 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1065 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1074 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1117 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2677 return do_log_reg(ctx, a, tcg_gen_andc_reg); in trans_andcm()
3419 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in do_depw_sar()
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| /dports/emulators/qemu5/qemu-5.2.0/target/hppa/ |
| H A D | translate.c | 127 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
221 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1047 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1065 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1074 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1117 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2679 return do_log_reg(ctx, a, tcg_gen_andc_reg); in trans_andcm()
3434 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in do_depw_sar()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/hppa/ |
| H A D | translate.c | 127 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
221 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1047 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1065 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1074 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1117 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2679 return do_log_reg(ctx, a, tcg_gen_andc_reg); in trans_andcm()
3434 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in do_depw_sar()
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/hppa/ |
| H A D | translate.c | 127 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
221 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1031 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1049 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1058 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1101 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2864 { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_reg },
3754 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in trans_depw_sar()
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| /dports/emulators/qemu42/qemu-4.2.1/target/hppa/ |
| H A D | translate.c | 127 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
221 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1047 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1065 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1074 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1117 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2677 return do_log_reg(ctx, a, tcg_gen_andc_reg); in trans_andcm()
3419 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in do_depw_sar()
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/hppa/ |
| H A D | translate.c | 124 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
218 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1017 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1035 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1044 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1087 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2637 return do_log_reg(ctx, a, tcg_gen_andc_reg); in trans_andcm()
3386 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in do_depw_sar()
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| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/hppa/ |
| H A D | translate.c | 127 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
221 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1047 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1065 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1074 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1117 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2677 return do_log_reg(ctx, a, tcg_gen_andc_reg); in trans_andcm()
3432 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in do_depw_sar()
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| /dports/emulators/qemu60/qemu-6.0.0/target/hppa/ |
| H A D | translate.c | 127 #define tcg_gen_andc_reg tcg_gen_andc_i64 macro
221 #define tcg_gen_andc_reg tcg_gen_andc_i32 macro
1047 tcg_gen_andc_reg(cb, cb, res); in do_unit_cond()
1065 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1074 tcg_gen_andc_reg(tmp, tmp, res); in do_unit_cond()
1117 tcg_gen_andc_reg(sv, sv, tmp); in do_add_sv()
2679 return do_log_reg(ctx, a, tcg_gen_andc_reg); in trans_andcm()
3434 tcg_gen_andc_reg(dest, cpu_gr[rs], mask); in do_depw_sar()
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