Home
last modified time | relevance | path

Searched refs:tcg_gen_sari_reg (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu/qemu-6.2.0/target/hppa/
H A Dtranslate.c96 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
191 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
866 tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); in do_cond()
2796 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()
/dports/emulators/qemu-utils/qemu-4.2.1/target/hppa/
H A Dtranslate.c99 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
194 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
900 tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); in do_cond()
2848 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()
/dports/emulators/qemu5/qemu-5.2.0/target/hppa/
H A Dtranslate.c99 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
194 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
900 tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); in do_cond()
2850 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/hppa/
H A Dtranslate.c99 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
194 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
900 tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); in do_cond()
2850 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()
/dports/emulators/qemu42/qemu-4.2.1/target/hppa/
H A Dtranslate.c99 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
194 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
900 tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); in do_cond()
2848 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/hppa/
H A Dtranslate.c96 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
191 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
870 tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); in do_cond()
2804 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/hppa/
H A Dtranslate.c99 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
194 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
900 tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); in do_cond()
2848 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()
/dports/emulators/qemu60/qemu-6.0.0/target/hppa/
H A Dtranslate.c99 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
194 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
900 tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); in do_cond()
2850 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/hppa/
H A Dtranslate.c99 #define tcg_gen_sari_reg tcg_gen_sari_i64 macro
194 #define tcg_gen_sari_reg tcg_gen_sari_i32 macro
2787 tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); in trans_ds()