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Searched refs:tes_sh_base (Results 1 – 11 of 11) sorted by relevance

/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.c79 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
103 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
111 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
287 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp531 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
548 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
556 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
764 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp520 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL]; in si_emit_derived_tess_state() local
537 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp && in si_emit_derived_tess_state()
545 sctx->last_tes_sh_base = tes_sh_base; in si_emit_derived_tess_state()
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()