| /dports/lang/clover/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
863 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
870 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
912 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1008 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1034 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 457 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_load_input_tes()
519 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_nir_store_output_tcs()
568 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in load_tess_level()
647 buffer_offset = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_copy_tcs_inputs()
798 base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset); in si_write_tess_factors()
867 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_llvm_emit_tcs_epilogue()
874 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR); in si_llvm_emit_tcs_epilogue()
916 ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2); in si_set_ls_return_value_for_tcs()
1012 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
1038 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); in si_llvm_build_tcs_epilog()
|
| /dports/lang/clover/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/libosmesa/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/mesa-libs/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/amd/common/ |
| H A D | ac_shader_args.h | 85 struct ac_arg tess_offchip_offset; member
|
| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_shader_args.c | 600 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
627 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
646 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
651 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
668 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
|
| /dports/graphics/mesa-libs/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_shader_args.c | 600 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
627 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
646 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
651 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
668 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_shader_args.c | 600 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
627 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
646 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
651 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
668 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_shader_args.c | 600 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
627 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
646 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
651 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
668 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
|
| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/amd/vulkan/ |
| H A D | radv_shader_args.c | 600 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
627 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
646 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
651 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
668 ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); in radv_declare_shader_args()
|