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Searched refs:timing_cfg (Results 1 – 25 of 100) sorted by relevance

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/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2162aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2162aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2162aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2162aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2162aqds/
H A Dddr_init.c35 .timing_cfg[0] = U(0xFFAA0018),
36 .timing_cfg[1] = U(0x646A8844),
37 .timing_cfg[2] = U(0x00058022),
38 .timing_cfg[3] = U(0x13622100),
39 .timing_cfg[4] = U(0x02),
40 .timing_cfg[5] = U(0x07401400),
41 .timing_cfg[7] = U(0x3BB00000),
42 .timing_cfg[8] = U(0x0944AC00),
86 .timing_cfg[0] = U(0xFF990018),
90 .timing_cfg[4] = U(0x02),
[all …]
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160ardb/
H A Dddr_init.c32 .timing_cfg[0] = U(0xFF550018),
33 .timing_cfg[1] = U(0xBAB48C42),
34 .timing_cfg[2] = U(0x48C111),
35 .timing_cfg[3] = U(0x10C1000),
36 .timing_cfg[4] = U(0x2),
37 .timing_cfg[5] = U(0x3401400),
38 .timing_cfg[7] = U(0x13300000),
39 .timing_cfg[8] = U(0x2114600),
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160ardb/
H A Dddr_init.c32 .timing_cfg[0] = U(0xFF550018),
33 .timing_cfg[1] = U(0xBAB48C42),
34 .timing_cfg[2] = U(0x48C111),
35 .timing_cfg[3] = U(0x10C1000),
36 .timing_cfg[4] = U(0x2),
37 .timing_cfg[5] = U(0x3401400),
38 .timing_cfg[7] = U(0x13300000),
39 .timing_cfg[8] = U(0x2114600),
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160ardb/
H A Dddr_init.c32 .timing_cfg[0] = U(0xFF550018),
33 .timing_cfg[1] = U(0xBAB48C42),
34 .timing_cfg[2] = U(0x48C111),
35 .timing_cfg[3] = U(0x10C1000),
36 .timing_cfg[4] = U(0x2),
37 .timing_cfg[5] = U(0x3401400),
38 .timing_cfg[7] = U(0x13300000),
39 .timing_cfg[8] = U(0x2114600),
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160ardb/
H A Dddr_init.c32 .timing_cfg[0] = U(0xFF550018),
33 .timing_cfg[1] = U(0xBAB48C42),
34 .timing_cfg[2] = U(0x48C111),
35 .timing_cfg[3] = U(0x10C1000),
36 .timing_cfg[4] = U(0x2),
37 .timing_cfg[5] = U(0x3401400),
38 .timing_cfg[7] = U(0x13300000),
39 .timing_cfg[8] = U(0x2114600),
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/nxp/soc-lx2160a/lx2160ardb/
H A Dddr_init.c32 .timing_cfg[0] = U(0xFF550018),
33 .timing_cfg[1] = U(0xBAB48C42),
34 .timing_cfg[2] = U(0x48C111),
35 .timing_cfg[3] = U(0x10C1000),
36 .timing_cfg[4] = U(0x2),
37 .timing_cfg[5] = U(0x3401400),
38 .timing_cfg[7] = U(0x13300000),
39 .timing_cfg[8] = U(0x2114600),
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/drivers/nxp/ddr/nxp-ddr/
H A Dregs.c228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) | in cal_timing_cfg()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]); in cal_timing_cfg()
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) | in cal_timing_cfg()
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]); in cal_timing_cfg()
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) | in cal_timing_cfg()
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) | in cal_timing_cfg()
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) | in cal_timing_cfg()
[all …]
H A Dddrc.c228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]); in ddrc_set_regs()
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]); in ddrc_set_regs()
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]); in ddrc_set_regs()
231 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]); in ddrc_set_regs()
232 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]); in ddrc_set_regs()
233 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]); in ddrc_set_regs()
234 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]); in ddrc_set_regs()
235 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]); in ddrc_set_regs()
236 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]); in ddrc_set_regs()
237 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]); in ddrc_set_regs()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/drivers/nxp/ddr/nxp-ddr/
H A Dregs.c228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) | in cal_timing_cfg()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]); in cal_timing_cfg()
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) | in cal_timing_cfg()
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]); in cal_timing_cfg()
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) | in cal_timing_cfg()
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) | in cal_timing_cfg()
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) | in cal_timing_cfg()
[all …]
H A Dddrc.c228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]); in ddrc_set_regs()
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]); in ddrc_set_regs()
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]); in ddrc_set_regs()
231 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]); in ddrc_set_regs()
232 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]); in ddrc_set_regs()
233 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]); in ddrc_set_regs()
234 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]); in ddrc_set_regs()
235 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]); in ddrc_set_regs()
236 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]); in ddrc_set_regs()
237 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]); in ddrc_set_regs()
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/drivers/nxp/ddr/nxp-ddr/
H A Dregs.c228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) | in cal_timing_cfg()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]); in cal_timing_cfg()
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) | in cal_timing_cfg()
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]); in cal_timing_cfg()
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) | in cal_timing_cfg()
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) | in cal_timing_cfg()
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) | in cal_timing_cfg()
[all …]
H A Dddrc.c228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]); in ddrc_set_regs()
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]); in ddrc_set_regs()
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]); in ddrc_set_regs()
231 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]); in ddrc_set_regs()
232 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]); in ddrc_set_regs()
233 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]); in ddrc_set_regs()
234 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]); in ddrc_set_regs()
235 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]); in ddrc_set_regs()
236 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]); in ddrc_set_regs()
237 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]); in ddrc_set_regs()
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/drivers/nxp/ddr/nxp-ddr/
H A Dregs.c228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) | in cal_timing_cfg()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]); in cal_timing_cfg()
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) | in cal_timing_cfg()
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]); in cal_timing_cfg()
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) | in cal_timing_cfg()
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) | in cal_timing_cfg()
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) | in cal_timing_cfg()
[all …]
H A Dddrc.c228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]); in ddrc_set_regs()
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]); in ddrc_set_regs()
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]); in ddrc_set_regs()
231 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]); in ddrc_set_regs()
232 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]); in ddrc_set_regs()
233 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]); in ddrc_set_regs()
234 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]); in ddrc_set_regs()
235 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]); in ddrc_set_regs()
236 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]); in ddrc_set_regs()
237 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]); in ddrc_set_regs()
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/drivers/nxp/ddr/nxp-ddr/
H A Dregs.c228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) | in cal_timing_cfg()
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]); in cal_timing_cfg()
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]); in cal_timing_cfg()
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]); in cal_timing_cfg()
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]); in cal_timing_cfg()
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) | in cal_timing_cfg()
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]); in cal_timing_cfg()
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) | in cal_timing_cfg()
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) | in cal_timing_cfg()
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) | in cal_timing_cfg()
[all …]
H A Dddrc.c228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]); in ddrc_set_regs()
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]); in ddrc_set_regs()
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]); in ddrc_set_regs()
231 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]); in ddrc_set_regs()
232 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]); in ddrc_set_regs()
233 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]); in ddrc_set_regs()
234 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]); in ddrc_set_regs()
235 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]); in ddrc_set_regs()
236 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]); in ddrc_set_regs()
237 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]); in ddrc_set_regs()

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