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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_altera_lpm.v3312 reg [lpm_widthn-1:0] tmp_quotient; register
3429 tmp_quotient = (sign_q == 1'b1) ? (~t_q + 1) : t_q;
3436 tmp_quotient = tmp_quotient + ((sign_d == 1'b1) ? 1 : -1 );
3454 quotient_pipe[pipe_ptr] <= tmp_quotient;
3463 assign quotient = (lpm_pipeline > 0) ? quotient_pipe[pipe_ptr] : tmp_quotient;