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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/
H A Daxi_ram_fifo_bist.v123 reg [COUNT_W-1:0] tx_count; // Number of words transmitted to FIFO register
157 .tx_count (tx_count),
199 if (stop || (tx_count == num_words_m1 && m_tvalid && m_tready && !continuous)) begin
209 if (rx_count >= tx_count) begin
236 tx_count <= 0;
247 tx_count <= tx_count + 1;
285 tx_count <= 0;
/dports/emulators/qemu42/qemu-4.2.1/hw/char/
H A Dcadence_uart.c133 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
160 s->tx_count = 0; in uart_tx_reset()
286 s->tx_count = 0; in cadence_uart_xmit()
290 if (!s->tx_count) { in cadence_uart_xmit()
297 s->tx_count -= ret; in cadence_uart_xmit()
301 if (s->tx_count) { in cadence_uart_xmit()
305 s->tx_count = 0; in cadence_uart_xmit()
322 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
332 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
333 s->tx_count += size; in uart_write_tx_fifo()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/char/
H A Dcadence_uart.c130 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
157 s->tx_count = 0; in uart_tx_reset()
283 s->tx_count = 0; in cadence_uart_xmit()
287 if (!s->tx_count) { in cadence_uart_xmit()
294 s->tx_count -= ret; in cadence_uart_xmit()
298 if (s->tx_count) { in cadence_uart_xmit()
302 s->tx_count = 0; in cadence_uart_xmit()
319 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
329 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
330 s->tx_count += size; in uart_write_tx_fifo()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/char/
H A Dcadence_uart.c133 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
160 s->tx_count = 0; in uart_tx_reset()
286 s->tx_count = 0; in cadence_uart_xmit()
290 if (!s->tx_count) { in cadence_uart_xmit()
297 s->tx_count -= ret; in cadence_uart_xmit()
301 if (s->tx_count) { in cadence_uart_xmit()
305 s->tx_count = 0; in cadence_uart_xmit()
322 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
332 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
333 s->tx_count += size; in uart_write_tx_fifo()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/char/
H A Dcadence_uart.c133 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
160 s->tx_count = 0;
286 s->tx_count = 0;
290 if (!s->tx_count) {
297 s->tx_count -= ret;
301 if (s->tx_count) {
305 s->tx_count = 0;
322 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
332 memcpy(s->tx_fifo + s->tx_count, buf, size);
333 s->tx_count += size;
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/char/
H A Dcadence_uart.c133 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
160 s->tx_count = 0; in uart_tx_reset()
286 s->tx_count = 0; in cadence_uart_xmit()
290 if (!s->tx_count) { in cadence_uart_xmit()
297 s->tx_count -= ret; in cadence_uart_xmit()
301 if (s->tx_count) { in cadence_uart_xmit()
305 s->tx_count = 0; in cadence_uart_xmit()
322 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
332 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
333 s->tx_count += size; in uart_write_tx_fifo()
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/char/
H A Dcadence_uart.c136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
163 s->tx_count = 0; in uart_tx_reset()
309 s->tx_count = 0; in cadence_uart_xmit()
313 if (!s->tx_count) { in cadence_uart_xmit()
320 s->tx_count -= ret; in cadence_uart_xmit()
324 if (s->tx_count) { in cadence_uart_xmit()
328 s->tx_count = 0; in cadence_uart_xmit()
345 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
355 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
356 s->tx_count += size; in uart_write_tx_fifo()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/hw/char/
H A Dcadence_uart.c136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
163 s->tx_count = 0; in uart_tx_reset()
299 s->tx_count = 0; in cadence_uart_xmit()
303 if (!s->tx_count) { in cadence_uart_xmit()
310 s->tx_count -= ret; in cadence_uart_xmit()
314 if (s->tx_count) { in cadence_uart_xmit()
318 s->tx_count = 0; in cadence_uart_xmit()
335 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
345 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
346 s->tx_count += size; in uart_write_tx_fifo()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/char/
H A Dcadence_uart.c135 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
162 s->tx_count = 0; in uart_tx_reset()
298 s->tx_count = 0; in cadence_uart_xmit()
302 if (!s->tx_count) { in cadence_uart_xmit()
309 s->tx_count -= ret; in cadence_uart_xmit()
313 if (s->tx_count) { in cadence_uart_xmit()
317 s->tx_count = 0; in cadence_uart_xmit()
334 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
344 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
345 s->tx_count += size; in uart_write_tx_fifo()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/char/
H A Dcadence_uart.c136 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0; in uart_update_status()
163 s->tx_count = 0; in uart_tx_reset()
309 s->tx_count = 0; in cadence_uart_xmit()
313 if (!s->tx_count) { in cadence_uart_xmit()
320 s->tx_count -= ret; in cadence_uart_xmit()
324 if (s->tx_count) { in cadence_uart_xmit()
328 s->tx_count = 0; in cadence_uart_xmit()
345 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count; in uart_write_tx_fifo()
355 memcpy(s->tx_fifo + s->tx_count, buf, size); in uart_write_tx_fifo()
356 s->tx_count += size; in uart_write_tx_fifo()
[all …]
/dports/net/freeswitch/freeswitch-1.10.3.-release/libs/unimrcp/libs/mpf/src/
H A Dmpf_context.c39 unsigned char tx_count; member
141 header_item->tx_count = 0; in mpf_context_create()
187 header_item->tx_count = 0; in mpf_context_termination_add()
222 header_item1->tx_count--; in mpf_context_termination_subtract()
229 header_item2->tx_count--; in mpf_context_termination_subtract()
270 header_item1->tx_count ++; in mpf_context_association_add()
279 header_item2->tx_count ++; in mpf_context_association_add()
311 header_item1->tx_count --; in mpf_context_association_remove()
318 header_item2->tx_count --; in mpf_context_association_remove()
355 header_item1->tx_count--; in mpf_context_associations_reset()
[all …]
/dports/net-p2p/qtum/qtum-mainnet-fastlane-v0.20.3/src/bench/
H A Dmempool_stress.cpp24 size_t tx_count; member
25 Available(CTransactionRef& ref, size_t tx_count) : ref(ref), tx_count(tx_count){} in Available()
60 tx.vin.back().scriptSig = CScript() << coin.tx_count; in ComplexMemPool()
61 tx.vin.back().scriptWitness.stack.push_back(CScriptNum(coin.tx_count).getvch()); in ComplexMemPool()
/dports/net-p2p/bitcoin-utils/bitcoin-22.0/src/bench/
H A Dmempool_stress.cpp25 size_t tx_count; member
26 Available(CTransactionRef& ref, size_t tx_count) : ref(ref), tx_count(tx_count){} in Available()
66 tx.vin.back().scriptSig = CScript() << coin.tx_count; in ComplexMemPool()
67 tx.vin.back().scriptWitness.stack.push_back(CScriptNum(coin.tx_count).getvch()); in ComplexMemPool()
/dports/net-p2p/bitcoin/bitcoin-22.0/src/bench/
H A Dmempool_stress.cpp25 size_t tx_count;
26 Available(CTransactionRef& ref, size_t tx_count) : ref(ref), tx_count(tx_count){} in MempoolEviction()
66 tx.vin.back().scriptSig = CScript() << coin.tx_count;
67 tx.vin.back().scriptWitness.stack.push_back(CScriptNum(coin.tx_count).getvch());
/dports/net-p2p/bitcoin-daemon/bitcoin-22.0/src/bench/
H A Dmempool_stress.cpp25 size_t tx_count; member
26 Available(CTransactionRef& ref, size_t tx_count) : ref(ref), tx_count(tx_count){} in Available()
66 tx.vin.back().scriptSig = CScript() << coin.tx_count; in ComplexMemPool()
67 tx.vin.back().scriptWitness.stack.push_back(CScriptNum(coin.tx_count).getvch()); in ComplexMemPool()
/dports/net-p2p/namecoin-utils/namecoin-core-nc0.21.0.1/src/bench/
H A Dmempool_stress.cpp25 size_t tx_count; member
26 Available(CTransactionRef& ref, size_t tx_count) : ref(ref), tx_count(tx_count){} in Available()
66 tx.vin.back().scriptSig = CScript() << coin.tx_count; in ComplexMemPool()
67 tx.vin.back().scriptWitness.stack.push_back(CScriptNum(coin.tx_count).getvch()); in ComplexMemPool()
/dports/net-p2p/namecoin/namecoin-core-nc0.21.0.1/src/bench/
H A Dmempool_stress.cpp25 size_t tx_count; member
26 Available(CTransactionRef& ref, size_t tx_count) : ref(ref), tx_count(tx_count){} in Available()
66 tx.vin.back().scriptSig = CScript() << coin.tx_count; in ComplexMemPool()
67 tx.vin.back().scriptWitness.stack.push_back(CScriptNum(coin.tx_count).getvch()); in ComplexMemPool()
/dports/net-p2p/namecoin-daemon/namecoin-core-nc0.21.0.1/src/bench/
H A Dmempool_stress.cpp25 size_t tx_count; member
26 Available(CTransactionRef& ref, size_t tx_count) : ref(ref), tx_count(tx_count){} in Available()
66 tx.vin.back().scriptSig = CScript() << coin.tx_count; in ComplexMemPool()
67 tx.vin.back().scriptWitness.stack.push_back(CScriptNum(coin.tx_count).getvch()); in ComplexMemPool()
/dports/databases/xtrabackup8/percona-xtrabackup-8.0.14/mysql-test/suite/ndb_ddl/
H A Dalter_inplace.test40 let $tx_count = `SELECT count(*) from $tx`;
41 if ($tx_count != 5)
43 echo Wrong number of rows, expected 5 got $tx_count;
72 let $tx_count = `SELECT count(*) from $tx`;
73 if ($tx_count != 5)
75 echo Wrong number of rows, expected 5 got $tx_count;
118 let $tx_count = `SELECT count(*) from $tx`;
119 if ($tx_count != 5)
121 echo Wrong number of rows, expected 5 got $tx_count;
/dports/emulators/qemu42/qemu-4.2.1/hw/net/
H A Dmipsnet.c35 uint32_t tx_count; member
51 s->tx_count = 0; in mipsnet_reset()
130 ret = s->tx_count; in mipsnet_ioport_read()
167 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; in mipsnet_ioport_write()
190 || (s->tx_written == s->tx_count)) { in mipsnet_ioport_write()
195 s->tx_count = s->tx_written = 0; in mipsnet_ioport_write()
220 VMSTATE_UINT32(tx_count, MIPSnetState),
/dports/emulators/qemu/qemu-6.2.0/hw/net/
H A Dmipsnet.c36 uint32_t tx_count; member
52 s->tx_count = 0; in mipsnet_reset()
135 ret = s->tx_count; in mipsnet_ioport_read()
172 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; in mipsnet_ioport_write()
195 || (s->tx_written == s->tx_count)) { in mipsnet_ioport_write()
200 s->tx_count = s->tx_written = 0; in mipsnet_ioport_write()
225 VMSTATE_UINT32(tx_count, MIPSnetState),
/dports/emulators/qemu60/qemu-6.0.0/hw/net/
H A Dmipsnet.c36 uint32_t tx_count; member
52 s->tx_count = 0; in mipsnet_reset()
135 ret = s->tx_count; in mipsnet_ioport_read()
172 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; in mipsnet_ioport_write()
195 || (s->tx_written == s->tx_count)) { in mipsnet_ioport_write()
200 s->tx_count = s->tx_written = 0; in mipsnet_ioport_write()
225 VMSTATE_UINT32(tx_count, MIPSnetState),
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/net/
H A Dmipsnet.c32 uint32_t tx_count; member
48 s->tx_count = 0; in mipsnet_reset()
127 ret = s->tx_count; in mipsnet_ioport_read()
164 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; in mipsnet_ioport_write()
187 || (s->tx_written == s->tx_count)) { in mipsnet_ioport_write()
192 s->tx_count = s->tx_written = 0; in mipsnet_ioport_write()
217 VMSTATE_UINT32(tx_count, MIPSnetState),
/dports/emulators/qemu5/qemu-5.2.0/hw/net/
H A Dmipsnet.c36 uint32_t tx_count; member
52 s->tx_count = 0; in mipsnet_reset()
135 ret = s->tx_count; in mipsnet_ioport_read()
172 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; in mipsnet_ioport_write()
195 || (s->tx_written == s->tx_count)) { in mipsnet_ioport_write()
200 s->tx_count = s->tx_written = 0; in mipsnet_ioport_write()
225 VMSTATE_UINT32(tx_count, MIPSnetState),
/dports/emulators/qemu-utils/qemu-4.2.1/hw/net/
H A Dmipsnet.c35 uint32_t tx_count; member
51 s->tx_count = 0; in mipsnet_reset()
130 ret = s->tx_count; in mipsnet_ioport_read()
167 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0; in mipsnet_ioport_write()
190 || (s->tx_written == s->tx_count)) { in mipsnet_ioport_write()
195 s->tx_count = s->tx_written = 0; in mipsnet_ioport_write()
220 VMSTATE_UINT32(tx_count, MIPSnetState),

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