| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vld4_lane_u64_indices_1.c | 7 uint64x1x4_t
8 f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v) in f_vld4_lane_u64()
10 uint64x1x4_t res; in f_vld4_lane_u64()
|
| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/arm/neon/ |
| H A D | vld4u64.c | 13 uint64x1x4_t out_uint64x1x4_t; in test_vld4u64()
|
| H A D | vld4_dupu64.c | 13 uint64x1x4_t out_uint64x1x4_t; in test_vld4_dupu64()
|
| /dports/lang/gcc48/gcc-4.8.5/gcc/testsuite/gcc.target/arm/neon/ |
| H A D | vld4_dupu64.c | 13 uint64x1x4_t out_uint64x1x4_t; in test_vld4_dupu64()
|
| H A D | vld4u64.c | 13 uint64x1x4_t out_uint64x1x4_t; in test_vld4u64()
|
| /dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/testsuite/gcc.target/arm/neon/ |
| H A D | vld4_dupu64.c | 13 uint64x1x4_t out_uint64x1x4_t; in test_vld4_dupu64()
|
| H A D | vld4u64.c | 13 uint64x1x4_t out_uint64x1x4_t; in test_vld4u64()
|
| /dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/arm/neon/ |
| H A D | vld4_dupu64.c | 13 uint64x1x4_t out_uint64x1x4_t; in test_vld4_dupu64()
|