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Searched refs:umin (Results 1 – 25 of 4856) sorted by relevance

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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/Analysis/CostModel/ARM/
H A Dreduce-umin.ll150 declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
151 declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
152 declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
153 declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
156 declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
169 declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
170 declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
171 declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
172 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
173 declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll308 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
311 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
314 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
327 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
331 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll307 declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
308 declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
309 declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>)
310 declare i64 @llvm.vector.reduce.umin.v8i64(<8 x i64>)
313 declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)
326 declare i8 @llvm.vector.reduce.umin.v2i8(<2 x i8>)
327 declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
328 declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)
329 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
330 declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll298 declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
299 declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
300 declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
301 declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
304 declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
317 declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
318 declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
319 declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
320 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
321 declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Analysis/CostModel/X86/
H A Dreduce-umin.ll298 declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
299 declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
300 declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
301 declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
304 declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
317 declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
318 declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
319 declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
320 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
321 declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/Analysis/CostModel/X86/
H A Dreduce-umin-widen.ll298 declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
299 declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
300 declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
301 declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
304 declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
317 declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
318 declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
319 declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
320 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
321 declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
H A Dreduce-umin.ll298 declare i64 @llvm.experimental.vector.reduce.umin.v1i64(<1 x i64>)
299 declare i64 @llvm.experimental.vector.reduce.umin.v2i64(<2 x i64>)
300 declare i64 @llvm.experimental.vector.reduce.umin.v4i64(<4 x i64>)
301 declare i64 @llvm.experimental.vector.reduce.umin.v8i64(<8 x i64>)
304 declare i32 @llvm.experimental.vector.reduce.umin.v2i32(<2 x i32>)
317 declare i8 @llvm.experimental.vector.reduce.umin.v2i8(<2 x i8>)
318 declare i8 @llvm.experimental.vector.reduce.umin.v4i8(<4 x i8>)
319 declare i8 @llvm.experimental.vector.reduce.umin.v8i8(<8 x i8>)
320 declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
321 declare i8 @llvm.experimental.vector.reduce.umin.v32i8(<32 x i8>)
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/AArch64/SVE/
H A Dumin.s10 umin z0.b, z0.b, #0 label
16 umin z31.b, z31.b, #255 label
22 umin z0.b, z0.b, #0 label
28 umin z31.b, z31.b, #255 label
34 umin z0.b, z0.b, #0 label
40 umin z31.b, z31.b, #255 label
46 umin z0.b, z0.b, #0 label
52 umin z31.b, z31.b, #255 label
92 umin z4.d, p7/m, z4.d, z31.d label
104 umin z4.d, p7/m, z4.d, z31.d label
[all …]

12345678910>>...195