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/dports/archivers/jzlib/jzlib-1.1.1/misc/
H A DREADME6 - mindtermsrc-v121-compression.patch
14 $ tar xzf mindtermsrc-v121.tgz
16 $ patch -p1 < mindtermsrc-v121-compression.patch
/dports/security/mindterm-binary/
H A D.license-catalog.mk5 _LICENSE_DISTFILES=mindterm-ssh.html mindtermbin-v121.zip
/dports/www/firefox/firefox-99.0/third_party/jpeg-xl/lib/jxl/
H A Dfast_dct16-inl.h152 int16x8_t v121 = vmlaq_n_s16(v121_tmp, v120, 5); in FastIDCT() local
154 int16x8_t v123 = vaddq_s16(v121, v122); in FastIDCT()
155 int16x8_t v124 = vsubq_s16(v122, v121); in FastIDCT()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll36 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
81 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
123 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
172 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll36 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
81 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
123 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
172 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll36 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
81 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
123 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
172 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll36 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
81 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
123 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
172 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
215 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll36 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
81 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
123 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
172 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
215 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll36 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
81 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
123 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
172 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
215 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll36 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
81 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
123 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
172 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
215 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll36 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
81 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
123 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
172 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
215 ,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Hexagon/
H A Dregisterscavenger-fail1.ll232 %v121 = phi i32 [ %v144, %b34 ], [ 0, %b29 ]
233 %v122 = mul i32 %v110, %v121
236 %v125 = sitofp i32 %v121 to double
273 %v144 = add i32 %v121, 1

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