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/dports/lang/halide/Halide-release_2019_08_27-2654-g664dc4993/apps/autoscheduler/
H A Dcost_model_schedule.h76 Var v207(updated_head1_filter.get_schedule().dims()[0].var); in do_cost_model_schedule()
394 .split(v207, v207, v207i, 8, TailStrategy::GuardWithIf) in do_cost_model_schedule()
404 .split(v207, v207, v207i, 8, TailStrategy::GuardWithIf) in do_cost_model_schedule()
406 .reorder(v207i, v207, v208i, v209i, v208, v209) in do_cost_model_schedule()
412 .split(v207, v207, v207i, 8, TailStrategy::GuardWithIf) in do_cost_model_schedule()
414 .reorder(v207i, v207, v208i, v209i, v208, v209) in do_cost_model_schedule()
420 .split(v207, v207, v207i, 8, TailStrategy::GuardWithIf) in do_cost_model_schedule()
422 .reorder(v207i, v207, v208i, v209i, v208, v209) in do_cost_model_schedule()
428 .split(v207, v207, v207i, 8, TailStrategy::GuardWithIf) in do_cost_model_schedule()
430 .reorder(v207i, v207, v208i, v209i, v208, v209) in do_cost_model_schedule()
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll44 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
89 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
131 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
180 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll44 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
89 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
131 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
180 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll44 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
89 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
131 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
180 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll44 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
89 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
131 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
180 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
223 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll44 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
89 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
131 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
180 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
223 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll44 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
89 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
131 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
180 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
223 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll44 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
89 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
131 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
180 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
223 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreserve-vgpr-for-sgpr-spill.ll44 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
89 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
131 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
180 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
223 ,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
/dports/sysutils/vector/lucet-d4fc14a03bdb99ac83173d27fddf1aca48412a86/wasmtime/cranelift/filetests/filetests/regalloc/
H A Dsolver-fixedconflict-var.clif77 v207 -> v809
78 v815 = ifcmp_imm v207, -1
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C38 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
69 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
112 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
146 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
183 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C38 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
69 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
112 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
146 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
183 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C38 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
69 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
112 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
146 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
183 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/lang/gcc48/gcc-4.8.5/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C38 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
69 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
112 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
146 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
183 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/g++.dg/eh/
H A Dpr29166.C39 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in doIt() local
70 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in doIt()
113 …register int v201=OFF+201,v202=OFF+202,v203=OFF+203,v204=OFF+204,v205=OFF+205,v206=OFF+206,v207=OF… in main() local
147 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()
184 sum +=v201+v202+v203+v204+v205+v206+v207+v208+v209+v210; in main()

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