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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinsertelement.large.ll9 ; GCN-NEXT: v_lshlrev_b32_e32 v68, 8, v0
15 ; GCN-NEXT: v_add_co_u32_e32 v2, vcc, v0, v68
31 ; GCN-NEXT: global_load_dwordx4 v[44:47], v68, s[0:1]
32 ; GCN-NEXT: global_load_dwordx4 v[48:51], v68, s[0:1] offset:16
33 ; GCN-NEXT: global_load_dwordx4 v[52:55], v68, s[0:1] offset:32
34 ; GCN-NEXT: global_load_dwordx4 v[56:59], v68, s[0:1] offset:48
35 ; GCN-NEXT: global_load_dwordx4 v[60:63], v68, s[0:1] offset:64
42 ; GCN-NEXT: global_load_dwordx4 v[0:3], v68, s[0:1] offset:128
47 ; GCN-NEXT: global_store_dwordx4 v68, v[0:3], s[2:3] offset:128
55 ; GCN-NEXT: global_store_dwordx4 v68, v[44:47], s[2:3]
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A Dinsertelement.large.ll9 ; GCN-NEXT: v_lshlrev_b32_e32 v68, 8, v0
15 ; GCN-NEXT: v_add_co_u32_e32 v2, vcc, v0, v68
31 ; GCN-NEXT: global_load_dwordx4 v[44:47], v68, s[0:1]
32 ; GCN-NEXT: global_load_dwordx4 v[48:51], v68, s[0:1] offset:16
33 ; GCN-NEXT: global_load_dwordx4 v[52:55], v68, s[0:1] offset:32
34 ; GCN-NEXT: global_load_dwordx4 v[56:59], v68, s[0:1] offset:48
35 ; GCN-NEXT: global_load_dwordx4 v[60:63], v68, s[0:1] offset:64
42 ; GCN-NEXT: global_load_dwordx4 v[0:3], v68, s[0:1] offset:128
47 ; GCN-NEXT: global_store_dwordx4 v68, v[0:3], s[2:3] offset:128
55 ; GCN-NEXT: global_store_dwordx4 v68, v[44:47], s[2:3]
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinsertelement.large.ll9 ; GCN-NEXT: v_lshlrev_b32_e32 v68, 8, v0
15 ; GCN-NEXT: v_add_co_u32_e32 v2, vcc, v0, v68
31 ; GCN-NEXT: global_load_dwordx4 v[44:47], v68, s[0:1]
32 ; GCN-NEXT: global_load_dwordx4 v[48:51], v68, s[0:1] offset:16
33 ; GCN-NEXT: global_load_dwordx4 v[52:55], v68, s[0:1] offset:32
34 ; GCN-NEXT: global_load_dwordx4 v[56:59], v68, s[0:1] offset:48
35 ; GCN-NEXT: global_load_dwordx4 v[60:63], v68, s[0:1] offset:64
42 ; GCN-NEXT: global_load_dwordx4 v[0:3], v68, s[0:1] offset:128
47 ; GCN-NEXT: global_store_dwordx4 v68, v[0:3], s[2:3] offset:128
55 ; GCN-NEXT: global_store_dwordx4 v68, v[44:47], s[2:3]
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinsertelement.large.ll9 ; GCN-NEXT: v_lshlrev_b32_e32 v68, 8, v0
15 ; GCN-NEXT: v_add_co_u32_e32 v2, vcc, v0, v68
31 ; GCN-NEXT: global_load_dwordx4 v[44:47], v68, s[0:1]
32 ; GCN-NEXT: global_load_dwordx4 v[48:51], v68, s[0:1] offset:16
33 ; GCN-NEXT: global_load_dwordx4 v[52:55], v68, s[0:1] offset:32
34 ; GCN-NEXT: global_load_dwordx4 v[56:59], v68, s[0:1] offset:48
35 ; GCN-NEXT: global_load_dwordx4 v[60:63], v68, s[0:1] offset:64
42 ; GCN-NEXT: global_load_dwordx4 v[0:3], v68, s[0:1] offset:128
47 ; GCN-NEXT: global_store_dwordx4 v68, v[0:3], s[2:3] offset:128
55 ; GCN-NEXT: global_store_dwordx4 v68, v[44:47], s[2:3]
[all …]
/dports/sysutils/vector/lucet-d4fc14a03bdb99ac83173d27fddf1aca48412a86/wasmtime/cranelift/filetests/filetests/regalloc/
H A Dcoloring-227.clif14 …15: i32, v17: i32, v25: i32, v31: i32, v40: i32, v47: i32, v54: i32, v61: i32, v68: i32, v75: i32):
60 [Op1jmpb#eb] jump block3(v25, v36, v25, v31, v40, v47, v54, v61, v68, v75)
66 [Op1jmpb#eb] jump block2(v40, v47, v54, v61, v68, v75)
H A Dspill-noregs.clif7 ; 'Ran out of GPR registers when inserting copy before v68 = icmp.i32 eq v66, v67',
81 v68 = icmp eq v66, v67
82 v69 = bint.i32 v68
/dports/lang/zig-devel/zig-0.9.0/lib/std/target/
H A Dhexagon.zig39 v68,
228 result[@enumToInt(Feature.v68)] = .{
229 .llvm_name = "v68",
420 .v68,
/dports/lang/zig/zig-0.9.0/lib/std/target/
H A Dhexagon.zig39 v68,
228 result[@enumToInt(Feature.v68)] = .{
229 .llvm_name = "v68",
420 .v68,
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
H A Dswp-bad-sched.ll105 %v57 = phi i32 [ %v68, %b7 ], [ %v51, %b6 ]
118 %v68 = add nsw i32 %v57, 1
119 %v69 = icmp eq i32 %v68, %a1
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll118 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
124 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
125 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
138 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
139 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll118 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
124 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
125 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
138 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
139 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll116 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
122 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
123 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
136 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
137 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Hexagon/
H A Dswp-conv3x3-nested.ll118 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
124 …%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %…
125 …%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %…
138 …%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %…
139 …%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %…
/dports/sysutils/vector/lucet-d4fc14a03bdb99ac83173d27fddf1aca48412a86/wasmtime/cranelift/filetests/filetests/legalizer/
H A Dbitrev-i128.clif85 ; check: v68 = ushr_imm v67, 32
87 ; check: v5 = bor v68, v69

12345678910>>...53