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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dshift-select.ll120 ; GCN-LABEL: name: v_ashr_i64
123 define amdgpu_kernel void @v_ashr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dshift-select.ll120 ; GCN-LABEL: name: v_ashr_i64
123 define amdgpu_kernel void @v_ashr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dshift-select.ll120 ; GCN-LABEL: name: v_ashr_i64
123 define amdgpu_kernel void @v_ashr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dsra.ll92 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
119 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
169 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dsbfx.ll80 define i64 @v_ashr_i64(i64 %value) {
81 ; GCN-LABEL: v_ashr_i64:
89 ; GFX10-LABEL: v_ashr_i64:
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A Dsbfx.ll80 define i64 @v_ashr_i64(i64 %value) {
81 ; GCN-LABEL: v_ashr_i64:
89 ; GFX10-LABEL: v_ashr_i64:
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dsbfx.ll80 define i64 @v_ashr_i64(i64 %value) {
81 ; GCN-LABEL: v_ashr_i64:
89 ; GFX10-LABEL: v_ashr_i64:
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dsbfx.ll80 define i64 @v_ashr_i64(i64 %value) {
81 ; GCN-LABEL: v_ashr_i64:
89 ; GFX10-LABEL: v_ashr_i64:
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dsbfx.ll80 define i64 @v_ashr_i64(i64 %value) {
81 ; GCN-LABEL: v_ashr_i64:
89 ; GFX10-LABEL: v_ashr_i64:
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_vop3_e64.s7434 v_ashr_i64 v[5:6], v[1:2], v2 label
7443 v_ashr_i64 v[5:6], s[2:3], v2 label
7455 v_ashr_i64 v[5:6], vcc, v2 label
7458 v_ashr_i64 v[5:6], tba, v2 label
7461 v_ashr_i64 v[5:6], tma, v2 label
7467 v_ashr_i64 v[5:6], exec, v2 label
7470 v_ashr_i64 v[5:6], 0, v2 label
7473 v_ashr_i64 v[5:6], -1, v2 label
7476 v_ashr_i64 v[5:6], 0.5, v2 label
7479 v_ashr_i64 v[5:6], -4.0, v2 label
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_vop3_e64.s7434 v_ashr_i64 v[5:6], v[1:2], v2 label
7443 v_ashr_i64 v[5:6], s[2:3], v2 label
7455 v_ashr_i64 v[5:6], vcc, v2 label
7458 v_ashr_i64 v[5:6], tba, v2 label
7461 v_ashr_i64 v[5:6], tma, v2 label
7467 v_ashr_i64 v[5:6], exec, v2 label
7470 v_ashr_i64 v[5:6], 0, v2 label
7473 v_ashr_i64 v[5:6], -1, v2 label
7476 v_ashr_i64 v[5:6], 0.5, v2 label
7479 v_ashr_i64 v[5:6], -4.0, v2 label
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_vop3_e64.s7434 v_ashr_i64 v[5:6], v[1:2], v2 label
7443 v_ashr_i64 v[5:6], s[2:3], v2 label
7455 v_ashr_i64 v[5:6], vcc, v2 label
7458 v_ashr_i64 v[5:6], tba, v2 label
7461 v_ashr_i64 v[5:6], tma, v2 label
7467 v_ashr_i64 v[5:6], exec, v2 label
7470 v_ashr_i64 v[5:6], 0, v2 label
7473 v_ashr_i64 v[5:6], -1, v2 label
7476 v_ashr_i64 v[5:6], 0.5, v2 label
7479 v_ashr_i64 v[5:6], -4.0, v2 label
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_vop3_e64.s7434 v_ashr_i64 v[5:6], v[1:2], v2 label
7443 v_ashr_i64 v[5:6], s[2:3], v2 label
7455 v_ashr_i64 v[5:6], vcc, v2 label
7458 v_ashr_i64 v[5:6], tba, v2 label
7461 v_ashr_i64 v[5:6], tma, v2 label
7467 v_ashr_i64 v[5:6], exec, v2 label
7470 v_ashr_i64 v[5:6], 0, v2 label
7473 v_ashr_i64 v[5:6], -1, v2 label
7476 v_ashr_i64 v[5:6], 0.5, v2 label
7479 v_ashr_i64 v[5:6], -4.0, v2 label
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_vop3_e64.s7434 v_ashr_i64 v[5:6], v[1:2], v2 label
7443 v_ashr_i64 v[5:6], s[2:3], v2 label
7455 v_ashr_i64 v[5:6], vcc, v2 label
7458 v_ashr_i64 v[5:6], tba, v2 label
7461 v_ashr_i64 v[5:6], tma, v2 label
7467 v_ashr_i64 v[5:6], exec, v2 label
7470 v_ashr_i64 v[5:6], 0, v2 label
7473 v_ashr_i64 v[5:6], -1, v2 label
7476 v_ashr_i64 v[5:6], 0.5, v2 label
7479 v_ashr_i64 v[5:6], -4.0, v2 label
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/AMDGPU/
H A Dgfx7_asm_vop3_e64.s7434 v_ashr_i64 v[5:6], v[1:2], v2 label
7443 v_ashr_i64 v[5:6], s[2:3], v2 label
7455 v_ashr_i64 v[5:6], vcc, v2 label
7458 v_ashr_i64 v[5:6], tba, v2 label
7461 v_ashr_i64 v[5:6], tma, v2 label
7467 v_ashr_i64 v[5:6], exec, v2 label
7470 v_ashr_i64 v[5:6], 0, v2 label
7473 v_ashr_i64 v[5:6], -1, v2 label
7476 v_ashr_i64 v[5:6], 0.5, v2 label
7479 v_ashr_i64 v[5:6], -4.0, v2 label
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_vop3_e64.s7434 v_ashr_i64 v[5:6], v[1:2], v2
7443 v_ashr_i64 v[5:6], s[2:3], v2
7455 v_ashr_i64 v[5:6], vcc, v2
7458 v_ashr_i64 v[5:6], tba, v2
7461 v_ashr_i64 v[5:6], tma, v2
7467 v_ashr_i64 v[5:6], exec, v2
7470 v_ashr_i64 v[5:6], 0, v2
7473 v_ashr_i64 v[5:6], -1, v2
7476 v_ashr_i64 v[5:6], 0.5, v2
7479 v_ashr_i64 v[5:6], -4.0, v2
[all …]

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