Home
last modified time | relevance | path

Searched refs:v_bfrev_b32_e32 (Results 1 – 25 of 250) sorted by relevance

12345678910

/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse.ll76 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
92 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
173 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
280 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
281 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
387 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
388 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
503 ; SI-NEXT: v_bfrev_b32_e32 v4, v2
504 ; SI-NEXT: v_bfrev_b32_e32 v3, v3
505 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
[all …]
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dbitreverse.ll76 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
92 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
173 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
280 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
281 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
387 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
388 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
503 ; SI-NEXT: v_bfrev_b32_e32 v4, v2
504 ; SI-NEXT: v_bfrev_b32_e32 v3, v3
505 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
[all …]
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse.ll76 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
92 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
173 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
280 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
281 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
387 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
388 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
503 ; SI-NEXT: v_bfrev_b32_e32 v4, v2
504 ; SI-NEXT: v_bfrev_b32_e32 v3, v3
505 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
[all …]
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse.ll76 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
92 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
173 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
280 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
281 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
387 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
388 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
503 ; SI-NEXT: v_bfrev_b32_e32 v4, v2
504 ; SI-NEXT: v_bfrev_b32_e32 v3, v3
505 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
[all …]
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse.ll76 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
92 ; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
173 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
280 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
281 ; SI-NEXT: v_bfrev_b32_e32 v0, v0
387 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
388 ; SI-NEXT: v_bfrev_b32_e32 v1, v1
503 ; SI-NEXT: v_bfrev_b32_e32 v4, v2
504 ; SI-NEXT: v_bfrev_b32_e32 v3, v3
505 ; SI-NEXT: v_bfrev_b32_e32 v2, v0
[all …]
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
H A Dsaddsat.ll78 ; GFX6-NEXT: v_bfrev_b32_e32 v0, 1
79 ; GFX6-NEXT: v_bfrev_b32_e32 v2, -2
92 ; GFX8-NEXT: v_bfrev_b32_e32 v0, 1
93 ; GFX8-NEXT: v_bfrev_b32_e32 v2, -2
331 ; GFX6-NEXT: v_bfrev_b32_e32 v4, 1
332 ; GFX6-NEXT: v_bfrev_b32_e32 v5, -2
352 ; GFX8-NEXT: v_bfrev_b32_e32 v4, 1
353 ; GFX8-NEXT: v_bfrev_b32_e32 v5, -2
385 ; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
402 ; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
[all …]
H A Dssubsat.ll78 ; GFX6-NEXT: v_bfrev_b32_e32 v0, 1
79 ; GFX6-NEXT: v_bfrev_b32_e32 v2, -2
92 ; GFX8-NEXT: v_bfrev_b32_e32 v0, 1
93 ; GFX8-NEXT: v_bfrev_b32_e32 v2, -2
332 ; GFX6-NEXT: v_bfrev_b32_e32 v4, 1
333 ; GFX6-NEXT: v_bfrev_b32_e32 v5, -2
353 ; GFX8-NEXT: v_bfrev_b32_e32 v4, 1
385 ; GFX6-NEXT: v_bfrev_b32_e32 v6, 1
413 ; GFX8-NEXT: v_bfrev_b32_e32 v6, 1
453 ; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
H A Dsaddsat.ll78 ; GFX6-NEXT: v_bfrev_b32_e32 v0, 1
79 ; GFX6-NEXT: v_bfrev_b32_e32 v2, -2
92 ; GFX8-NEXT: v_bfrev_b32_e32 v0, 1
93 ; GFX8-NEXT: v_bfrev_b32_e32 v2, -2
331 ; GFX6-NEXT: v_bfrev_b32_e32 v4, 1
332 ; GFX6-NEXT: v_bfrev_b32_e32 v5, -2
352 ; GFX8-NEXT: v_bfrev_b32_e32 v4, 1
353 ; GFX8-NEXT: v_bfrev_b32_e32 v5, -2
385 ; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
402 ; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
[all …]
H A Dssubsat.ll78 ; GFX6-NEXT: v_bfrev_b32_e32 v0, 1
79 ; GFX6-NEXT: v_bfrev_b32_e32 v2, -2
92 ; GFX8-NEXT: v_bfrev_b32_e32 v0, 1
93 ; GFX8-NEXT: v_bfrev_b32_e32 v2, -2
332 ; GFX6-NEXT: v_bfrev_b32_e32 v4, 1
333 ; GFX6-NEXT: v_bfrev_b32_e32 v5, -2
353 ; GFX8-NEXT: v_bfrev_b32_e32 v4, 1
385 ; GFX6-NEXT: v_bfrev_b32_e32 v6, 1
413 ; GFX8-NEXT: v_bfrev_b32_e32 v6, 1
453 ; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
H A Dsaddsat.ll78 ; GFX6-NEXT: v_bfrev_b32_e32 v0, 1
79 ; GFX6-NEXT: v_bfrev_b32_e32 v2, -2
92 ; GFX8-NEXT: v_bfrev_b32_e32 v0, 1
93 ; GFX8-NEXT: v_bfrev_b32_e32 v2, -2
331 ; GFX6-NEXT: v_bfrev_b32_e32 v4, 1
332 ; GFX6-NEXT: v_bfrev_b32_e32 v5, -2
352 ; GFX8-NEXT: v_bfrev_b32_e32 v4, 1
353 ; GFX8-NEXT: v_bfrev_b32_e32 v5, -2
385 ; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
402 ; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dbitreverse-inline-immediates.ll42 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
51 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
59 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
68 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
93 ; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
102 ; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}

12345678910