| /dports/devel/llvm90/llvm-9.0.1.src/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
270 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx10_asm_dpp16.s | 81 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
381 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 label
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
270 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx10_asm_dpp16.s | 81 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
381 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 label
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
270 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx10_asm_dpp16.s | 81 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
381 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 label
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx8_asm_vop1.s | 6039 v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
6051 v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
6054 v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
6057 v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
6060 v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
6063 v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 label
6066 v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 label
6069 v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 label
6075 v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 label
6090 v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
|
| H A D | gfx10_asm_dpp16.s | 84 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
384 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 label
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx8_asm_vop1.s | 6039 v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
6051 v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
6054 v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
6057 v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
6060 v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
6063 v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 label
6066 v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 label
6069 v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 label
6075 v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 label
6090 v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
|
| H A D | gfx10_asm_dpp16.s | 81 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 label
381 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 label
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
270 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx8_asm_vop1.s | 6039 v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
6051 v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
6054 v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
6057 v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
6060 v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
6063 v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 label
6066 v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 label
6069 v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 label
6075 v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 label
6090 v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
270 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx8_asm_vop1.s | 6039 v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
6051 v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
6054 v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
6057 v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
6060 v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
6063 v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 label
6066 v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 label
6069 v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 label
6075 v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 label
6090 v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx8_asm_vop1.s | 6039 v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
6051 v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
6054 v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
6057 v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
6060 v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
6063 v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 label
6066 v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 label
6069 v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 label
6075 v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 label
6090 v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] label
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 label
|
| H A D | gfx8_asm_vop1.s | 6039 v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
6051 v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
6054 v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
6057 v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
6060 v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
6063 v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 label
6066 v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 label
6069 v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 label
6075 v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 label
6090 v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/ |
| H A D | gfx10_asm_dpp8.s | 15 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7]
267 v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1
|
| H A D | gfx8_asm_vop1.s | 6039 v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 label
6051 v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 label
6054 v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 label
6057 v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 label
6060 v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 label
6063 v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 label
6066 v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 label
6069 v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 label
6075 v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 label
6090 v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 label
[all …]
|