Home
last modified time | relevance | path

Searched refs:v_lshl_add_u32 (Results 1 – 25 of 278) sorted by relevance

12345678910>>...12

/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
48 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
65 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
70 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
87 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
92 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
109 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
114 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
H A Dhip.extern.shared.array.ll26 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
53 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
68 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
84 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
85 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
103 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
104 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
122 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
123 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
48 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
65 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
70 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
87 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
92 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
109 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
114 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
H A Dhip.extern.shared.array.ll26 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
53 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
68 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
84 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
85 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
103 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
104 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
122 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
123 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
48 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
65 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
70 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
87 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
92 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
109 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
114 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
H A Dhip.extern.shared.array.ll26 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
53 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
68 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
84 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
85 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
103 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
104 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
122 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
123 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
48 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
65 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
70 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
87 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
92 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
109 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
114 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
H A Dhip.extern.shared.array.ll26 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
53 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
68 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
84 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
85 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
103 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
104 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
122 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
123 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
48 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
65 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
70 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
87 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
92 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
109 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
114 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
H A Dhip.extern.shared.array.ll26 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
53 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
68 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
84 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
85 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
103 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
104 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
122 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
123 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
48 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
65 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
70 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
87 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
92 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
109 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
114 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
H A Dhip.extern.shared.array.ll26 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
53 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
68 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
84 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
85 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
103 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
104 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
122 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
123 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
48 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
65 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
70 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
87 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
92 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
109 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
114 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
H A Dhip.extern.shared.array.ll26 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
53 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
68 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
84 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
85 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
103 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
104 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
122 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
123 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
49 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
67 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
72 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
90 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
95 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
113 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
118 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
H A Dhip.extern.shared.array.ll26 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
53 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
68 ; CHECK: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
84 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
85 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
103 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
104 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
122 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 2, [[DYNLDS]]
123 ; CHECK-DAG: v_lshl_add_u32 {{v[0-9]+}}, {{v[0-9]+}}, 3, [[DYNLDS]]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
49 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
67 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
72 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
90 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
95 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
113 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
118 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
49 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
67 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
72 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
90 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
95 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
113 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
118 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
49 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
67 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
72 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
90 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
95 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
113 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
118 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
49 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
67 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
72 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
90 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
95 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
113 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
118 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dshl_add.ll19 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
24 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
49 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3
67 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2
72 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2
90 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, s2
95 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2
113 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1
118 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/AMDGPU/
H A Delf-lds.s9 v_lshl_add_u32 v3, v0, 2, s0
13 v_lshl_add_u32 v3, v0, 2, s0
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/AMDGPU/
H A Delf-lds.s9 v_lshl_add_u32 v3, v0, 2, s0
13 v_lshl_add_u32 v3, v0, 2, s0
/dports/devel/llvm11/llvm-11.0.1.src/test/MC/AMDGPU/
H A Delf-lds.s9 v_lshl_add_u32 v3, v0, 2, s0
13 v_lshl_add_u32 v3, v0, 2, s0
/dports/devel/llvm10/llvm-10.0.1.src/test/MC/AMDGPU/
H A Delf-lds.s9 v_lshl_add_u32 v3, v0, 2, s0
13 v_lshl_add_u32 v3, v0, 2, s0

12345678910>>...12