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Searched refs:v_lshr_b64 (Results 1 – 25 of 312) sorted by relevance

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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dsdivrem64.ll105 ;SI-NOT: v_lshr_b64
122 ;SI-NOT: v_lshr_b64
142 ;SI-NOT: v_lshr_b64
162 ;SI-NOT: v_lshr_b64
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dudivrem64.ll106 ;SI-NOT: v_lshr_b64
123 ;SI-NOT: v_lshr_b64
141 ;SI-NOT: v_lshr_b64
160 ;SI-NOT: v_lshr_b64
H A Dshift-i128.ll10 ; GCN-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
34 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
40 ; GCN-NEXT: v_lshr_b64 v[5:6], v[2:3], v5
42 ; GCN-NEXT: v_lshr_b64 v[2:3], v[2:3], v4
60 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
132 ; GCN-NEXT: v_lshr_b64 v[2:3], 17, v1
155 ; GCN-NEXT: v_lshr_b64 v[1:2], s[4:5], v0
174 ; GCN-NEXT: v_lshr_b64 v[1:2], 33, v0
379 ; GCN-NEXT: v_lshr_b64 v[9:10], v[6:7], v9
384 ; GCN-NEXT: v_lshr_b64 v[2:3], v[2:3], v8
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dsdivrem64.ll105 ;SI-NOT: v_lshr_b64
122 ;SI-NOT: v_lshr_b64
142 ;SI-NOT: v_lshr_b64
162 ;SI-NOT: v_lshr_b64
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dudivrem64.ll106 ;SI-NOT: v_lshr_b64
123 ;SI-NOT: v_lshr_b64
141 ;SI-NOT: v_lshr_b64
160 ;SI-NOT: v_lshr_b64
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dsdivrem64.ll105 ;SI-NOT: v_lshr_b64
122 ;SI-NOT: v_lshr_b64
142 ;SI-NOT: v_lshr_b64
162 ;SI-NOT: v_lshr_b64
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dshift-i128.ll10 ; GCN-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
34 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
40 ; GCN-NEXT: v_lshr_b64 v[5:6], v[2:3], v5
42 ; GCN-NEXT: v_lshr_b64 v[2:3], v[2:3], v4
60 ; GCN-NEXT: v_lshr_b64 v[7:8], v[0:1], v4
101 ; GCN-NEXT: v_lshr_b64 v[0:1], v[2:3], 1
130 ; GCN-NEXT: v_lshr_b64 v[1:2], 17, v1
152 ; GCN-NEXT: v_lshr_b64 v[2:3], s[6:7], v0
171 ; GCN-NEXT: v_lshr_b64 v[2:3], 33, v0
376 ; GCN-NEXT: v_lshr_b64 v[9:10], v[6:7], v9
[all …]
H A Dudivrem64.ll106 ;SI-NOT: v_lshr_b64
123 ;SI-NOT: v_lshr_b64
141 ;SI-NOT: v_lshr_b64
160 ;SI-NOT: v_lshr_b64
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dsdivrem64.ll105 ;SI-NOT: v_lshr_b64
122 ;SI-NOT: v_lshr_b64
142 ;SI-NOT: v_lshr_b64
162 ;SI-NOT: v_lshr_b64
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dudivrem64.ll106 ;SI-NOT: v_lshr_b64
123 ;SI-NOT: v_lshr_b64
141 ;SI-NOT: v_lshr_b64
160 ;SI-NOT: v_lshr_b64
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dsdivrem64.ll105 ;SI-NOT: v_lshr_b64
122 ;SI-NOT: v_lshr_b64
142 ;SI-NOT: v_lshr_b64
162 ;SI-NOT: v_lshr_b64
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dudivrem64.ll106 ;SI-NOT: v_lshr_b64
123 ;SI-NOT: v_lshr_b64
141 ;SI-NOT: v_lshr_b64
160 ;SI-NOT: v_lshr_b64
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dshift-i128.ll10 ; GCN-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
34 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
40 ; GCN-NEXT: v_lshr_b64 v[5:6], v[2:3], v5
42 ; GCN-NEXT: v_lshr_b64 v[2:3], v[2:3], v4
60 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
128 ; GCN-NEXT: v_lshr_b64 v[2:3], 17, v1
151 ; GCN-NEXT: v_lshr_b64 v[1:2], s[4:5], v0
170 ; GCN-NEXT: v_lshr_b64 v[1:2], 33, v0
318 ; GCN-NEXT: v_lshr_b64 v[9:10], v[4:5], v9
375 ; GCN-NEXT: v_lshr_b64 v[9:10], v[6:7], v9
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
H A Dshift-i128.ll10 ; GCN-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
34 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
40 ; GCN-NEXT: v_lshr_b64 v[5:6], v[2:3], v5
42 ; GCN-NEXT: v_lshr_b64 v[2:3], v[2:3], v4
60 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
128 ; GCN-NEXT: v_lshr_b64 v[2:3], 17, v1
151 ; GCN-NEXT: v_lshr_b64 v[1:2], s[4:5], v0
170 ; GCN-NEXT: v_lshr_b64 v[1:2], 33, v0
318 ; GCN-NEXT: v_lshr_b64 v[9:10], v[4:5], v9
375 ; GCN-NEXT: v_lshr_b64 v[9:10], v[6:7], v9
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsrl.ll63 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
87 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
88 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
125 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
126 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
127 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
128 ; SI: v_lshr_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dshift-i128.ll10 ; GCN-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
34 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
40 ; GCN-NEXT: v_lshr_b64 v[5:6], v[2:3], v5
43 ; GCN-NEXT: v_lshr_b64 v[2:3], v[2:3], v4
60 ; GCN-NEXT: v_lshr_b64 v[5:6], v[0:1], v4
128 ; GCN-NEXT: v_lshr_b64 v[2:3], 17, v1
150 ; GCN-NEXT: v_lshr_b64 v[1:2], s[4:5], v0
169 ; GCN-NEXT: v_lshr_b64 v[1:2], 33, v0
323 ; GCN-NEXT: v_lshr_b64 v[9:10], v[4:5], v9
380 ; GCN-NEXT: v_lshr_b64 v[9:10], v[6:7], v9
[all …]

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