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Searched refs:v_lshrrev_b32_e64 (Results 1 – 25 of 256) sorted by relevance

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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll12 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s32
33 ; GFX9: v_lshrrev_b32_e64 v0, 6, s32
35 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
55 ; GFX9: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
74 ; GFX9: v_lshrrev_b32_e64 v0, 6, s32
109 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
140 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
173 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
196 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
251 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
H A Dstack-realign.ll13 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32
203 ; GCN-NEXT: v_lshrrev_b32_e64 [[VGPR_REG:v[0-9]+]], 6, s34
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll12 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s32
33 ; GFX9: v_lshrrev_b32_e64 v0, 6, s32
35 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
55 ; GFX9: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
74 ; GFX9: v_lshrrev_b32_e64 v0, 6, s32
109 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
140 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
173 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
196 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
251 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
H A Dstack-realign.ll13 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32
203 ; GCN-NEXT: v_lshrrev_b32_e64 [[VGPR_REG:v[0-9]+]], 6, s34
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
16 ; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
85 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
123 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
159 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
194 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
220 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
[all …]
H A Dlocal-stack-alloc-block-sp-reference.ll114 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33
129 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33
H A Dstack-realign.ll13 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32
201 ; GCN-NEXT: v_lshrrev_b32_e64 [[VGPR_REG:v[0-9]+]], 6, s34
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
16 ; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
87 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
125 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
161 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
196 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
222 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
[all …]
H A Dstack-realign.ll13 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32
200 ; GCN-NEXT: v_lshrrev_b32_e64 [[VGPR_REG:v[0-9]+]], 6, s34
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
16 ; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
87 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
125 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
161 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
196 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
222 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
16 ; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
87 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
125 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
161 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
196 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
222 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
16 ; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
85 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
123 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
159 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
194 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
220 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
[all …]
H A Dstack-realign.ll13 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32
202 ; GCN-NEXT: v_lshrrev_b32_e64 [[VGPR_REG:v[0-9]+]], 6, s34
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
16 ; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
87 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
125 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
161 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
196 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
222 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
16 ; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
85 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
123 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
159 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
194 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
220 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
[all …]
H A Dstack-realign.ll13 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32
202 ; GCN-NEXT: v_lshrrev_b32_e64 [[VGPR_REG:v[0-9]+]], 6, s34
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
16 ; GFX9-FLATSCR-NOT: v_lshrrev_b32_e64
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
87 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
125 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
161 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
196 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
222 ; GFX9-MUBUF-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB]]
38 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB0]]
39 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB1]]
61 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB]]
82 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB]]
118 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
150 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
184 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB]]
208 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]
264 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
H A Dstack-realign.ll14 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, [[SUB]]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB]]
38 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB0]]
39 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB1]]
61 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB]]
82 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB]]
118 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
150 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
184 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB]]
208 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]
264 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
H A Dstack-realign.ll14 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, [[SUB]]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll13 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB]]
38 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB]]
42 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB]]
63 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB]]
84 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, [[SUB]]
120 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
152 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
186 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[SUB]]
210 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]
266 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
H A Dstack-realign.ll14 ; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, [[SUB]]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll15 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
37 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
60 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
99 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
137 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
172 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
196 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll15 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
37 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
60 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
99 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
137 ; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
172 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
196 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]

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