/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/ |
H A D | sdivrem64.ll | 106 ;VI-NOT: v_lshrrev_b64 123 ;VI-NOT: v_lshrrev_b64 143 ;VI-NOT: v_lshrrev_b64 163 ;VI-NOT: v_lshrrev_b64
|
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/ |
H A D | sdivrem64.ll | 106 ;VI-NOT: v_lshrrev_b64 123 ;VI-NOT: v_lshrrev_b64 143 ;VI-NOT: v_lshrrev_b64 163 ;VI-NOT: v_lshrrev_b64
|
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/ |
H A D | sdivrem64.ll | 106 ;VI-NOT: v_lshrrev_b64 123 ;VI-NOT: v_lshrrev_b64 143 ;VI-NOT: v_lshrrev_b64 163 ;VI-NOT: v_lshrrev_b64
|
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/ |
H A D | sdivrem64.ll | 106 ;VI-NOT: v_lshrrev_b64 123 ;VI-NOT: v_lshrrev_b64 143 ;VI-NOT: v_lshrrev_b64 163 ;VI-NOT: v_lshrrev_b64
|
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/ |
H A D | sdivrem64.ll | 106 ;VI-NOT: v_lshrrev_b64 123 ;VI-NOT: v_lshrrev_b64 143 ;VI-NOT: v_lshrrev_b64 163 ;VI-NOT: v_lshrrev_b64
|
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/ |
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/ |
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/ |
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | srl.ll | 64 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 90 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 91 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 130 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 131 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 132 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 133 ; VI: v_lshrrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
|
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-shift-shrink.ll | 18 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 50 ; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1] 119 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1] 131 ; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
|