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Searched refs:v_mov_b32 (Results 1 – 25 of 795) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll87 ; VI: v_mov_b32 {{v[0-9]+}}, 64
95 ; VI: v_mov_b32 {{v[0-9]+}}, -16
164 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
171 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
291 ; VI: v_mov_b32 {{v[0-9]+}}, -4
357 ; VI: v_mov_b32 {{v[0-9]+}}, 64
365 ; VI: v_mov_b32 {{v[0-9]+}}, -16
454 ; VI: v_mov_b32 {{v[0-9]+}}, -4
512 ; VI: v_mov_b32 {{v[0-9]+}}, -1
629 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll87 ; VI: v_mov_b32 {{v[0-9]+}}, 64
95 ; VI: v_mov_b32 {{v[0-9]+}}, -16
164 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
171 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
291 ; VI: v_mov_b32 {{v[0-9]+}}, -4
357 ; VI: v_mov_b32 {{v[0-9]+}}, 64
365 ; VI: v_mov_b32 {{v[0-9]+}}, -16
454 ; VI: v_mov_b32 {{v[0-9]+}}, -4
512 ; VI: v_mov_b32 {{v[0-9]+}}, -1
629 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll87 ; VI: v_mov_b32 {{v[0-9]+}}, 64
95 ; VI: v_mov_b32 {{v[0-9]+}}, -16
164 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
171 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
291 ; VI: v_mov_b32 {{v[0-9]+}}, -4
357 ; VI: v_mov_b32 {{v[0-9]+}}, 64
365 ; VI: v_mov_b32 {{v[0-9]+}}, -16
454 ; VI: v_mov_b32 {{v[0-9]+}}, -4
512 ; VI: v_mov_b32 {{v[0-9]+}}, -1
629 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll84 ; VI: v_mov_b32 {{v[0-9]+}}, 64
92 ; VI: v_mov_b32 {{v[0-9]+}}, -16
161 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
168 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
288 ; VI: v_mov_b32 {{v[0-9]+}}, -4
354 ; VI: v_mov_b32 {{v[0-9]+}}, 64
362 ; VI: v_mov_b32 {{v[0-9]+}}, -16
451 ; VI: v_mov_b32 {{v[0-9]+}}, -4
509 ; VI: v_mov_b32 {{v[0-9]+}}, -1
626 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll84 ; VI: v_mov_b32 {{v[0-9]+}}, 64
92 ; VI: v_mov_b32 {{v[0-9]+}}, -16
161 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
168 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
288 ; VI: v_mov_b32 {{v[0-9]+}}, -4
354 ; VI: v_mov_b32 {{v[0-9]+}}, 64
362 ; VI: v_mov_b32 {{v[0-9]+}}, -16
451 ; VI: v_mov_b32 {{v[0-9]+}}, -4
509 ; VI: v_mov_b32 {{v[0-9]+}}, -1
626 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll87 ; VI: v_mov_b32 {{v[0-9]+}}, 64
95 ; VI: v_mov_b32 {{v[0-9]+}}, -16
164 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
171 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
291 ; VI: v_mov_b32 {{v[0-9]+}}, -4
357 ; VI: v_mov_b32 {{v[0-9]+}}, 64
365 ; VI: v_mov_b32 {{v[0-9]+}}, -16
454 ; VI: v_mov_b32 {{v[0-9]+}}, -4
512 ; VI: v_mov_b32 {{v[0-9]+}}, -1
629 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll84 ; VI: v_mov_b32 {{v[0-9]+}}, 64
92 ; VI: v_mov_b32 {{v[0-9]+}}, -16
161 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
168 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
288 ; VI: v_mov_b32 {{v[0-9]+}}, -4
354 ; VI: v_mov_b32 {{v[0-9]+}}, 64
362 ; VI: v_mov_b32 {{v[0-9]+}}, -16
451 ; VI: v_mov_b32 {{v[0-9]+}}, -4
509 ; VI: v_mov_b32 {{v[0-9]+}}, -1
626 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll84 ; VI: v_mov_b32 {{v[0-9]+}}, 64
92 ; VI: v_mov_b32 {{v[0-9]+}}, -16
161 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
168 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
288 ; VI: v_mov_b32 {{v[0-9]+}}, -4
354 ; VI: v_mov_b32 {{v[0-9]+}}, 64
362 ; VI: v_mov_b32 {{v[0-9]+}}, -16
451 ; VI: v_mov_b32 {{v[0-9]+}}, -4
509 ; VI: v_mov_b32 {{v[0-9]+}}, -1
626 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll87 ; VI: v_mov_b32 {{v[0-9]+}}, 64
95 ; VI: v_mov_b32 {{v[0-9]+}}, -16
164 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
171 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
291 ; VI: v_mov_b32 {{v[0-9]+}}, -4
357 ; VI: v_mov_b32 {{v[0-9]+}}, 64
365 ; VI: v_mov_b32 {{v[0-9]+}}, -16
454 ; VI: v_mov_b32 {{v[0-9]+}}, -4
512 ; VI: v_mov_b32 {{v[0-9]+}}, -1
629 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dinline-constraints.ll84 ; VI: v_mov_b32 {{v[0-9]+}}, 64
92 ; VI: v_mov_b32 {{v[0-9]+}}, -16
161 ; GCN: v_mov_b32 {{v[0-9]+}}, -16
168 ; GCN: v_mov_b32 {{v[0-9]+}}, 1
288 ; VI: v_mov_b32 {{v[0-9]+}}, -4
354 ; VI: v_mov_b32 {{v[0-9]+}}, 64
362 ; VI: v_mov_b32 {{v[0-9]+}}, -16
451 ; VI: v_mov_b32 {{v[0-9]+}}, -4
509 ; VI: v_mov_b32 {{v[0-9]+}}, -1
626 ; VI: v_mov_b32 {{v[0-9]+}}, -4
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/llvm10/llvm-10.0.1.src/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/llvm11/llvm-11.0.1.src/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/llvm90/llvm-9.0.1.src/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/llvm80/llvm-8.0.1.src/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/llvm70/llvm-7.0.1.src/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dvop_dpp_expr.s8 v_mov_b32 v0, v0 quad_perm:[0+zero,zero-2+two*two,1/one,1] label
11 v_mov_b32 v0, v0 row_shl:two-1 label
14 v_mov_b32 v0, v0 row_shr:0xe+one label
17 v_mov_b32 v0, v0 row_ror:0x6*two label
20 v_mov_b32 v0, v0 wave_shl:two/2 label
23 v_mov_b32 v0, v0 wave_rol:two-one label
26 v_mov_b32 v0, v0 wave_shr:1+zero label
29 v_mov_b32 v0, v0 wave_ror:two*2-3 label
32 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3) label
35 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1 label

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