v_mov_b32_dpp (reference) in projects: dports

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Searched refs:v_mov_b32_dpp (Results 1 – 25 of 318) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/llvm10/llvm-10.0.1.src/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/llvm11/llvm-11.0.1.src/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/llvm90/llvm-9.0.1.src/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/AMDGPU/
H A D	dpp-err.s	8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 label 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 label 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 label 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 label 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 label 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 label 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 label 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1 label
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A D	dpp-err.s	`8 v_mov_b32_dpp v0, v1 row_share:1 row_mask:0x1 bank_mask:0x1 12 v_mov_b32_dpp v0, v1 row_xmask:1 row_mask:0x1 bank_mask:0x1 16 v_mov_b32_dpp v0, v1 wave_shl:1 row_mask:0x1 bank_mask:0x1 20 v_mov_b32_dpp v0, v1 wave_shr:1 row_mask:0x1 bank_mask:0x1 24 v_mov_b32_dpp v0, v1 wave_rol:1 row_mask:0x1 bank_mask:0x1 28 v_mov_b32_dpp v0, v1 wave_ror:1 row_mask:0x1 bank_mask:0x1 32 v_mov_b32_dpp v0, v1 row_bcast:15 row_mask:0x1 bank_mask:0x1 36 v_mov_b32_dpp v0, v1 row_bcast:31 row_mask:0x1 bank_mask:0x1`
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	23 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 24 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 26 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 27 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 42 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 44 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 71 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 72 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 84 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 85 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	23 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 24 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 26 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 27 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 42 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 44 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 71 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 72 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 84 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 85 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	23 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 24 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 26 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 27 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 42 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 44 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 71 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 72 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 84 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 85 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	23 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 24 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 26 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 27 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 42 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 44 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 71 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 72 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 84 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 85 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	23 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 24 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 26 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 27 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 42 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 44 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 71 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 72 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 84 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 85 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	23 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 24 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 26 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 27 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 42 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 44 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 71 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 72 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 84 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 85 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	23 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 24 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 26 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 27 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 42 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 44 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 71 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 72 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 84 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 85 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	23 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 24 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 26 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 27 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 42 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 44 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 71 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 72 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 84 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 85 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	27 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 28 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 32 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 33 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 50 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 54 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 81 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 82 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 94 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 95 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	27 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 28 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 32 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 33 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 50 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 54 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 81 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 82 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 94 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 95 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	27 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 28 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 32 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 33 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 50 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 54 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 81 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 82 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 94 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 95 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A D	llvm.amdgcn.mov.dpp.ll	27 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c… 28 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 32 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound… 33 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 50 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou… 54 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctr… 81 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 82 ; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 94 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 95 ; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 [all …]

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