/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 32 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 54 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 55 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 32 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 54 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 55 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 32 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 54 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 55 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 32 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 54 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 55 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 32 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 54 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 55 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 32 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 54 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 248 ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] [all …]
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H A D | image-sample-waterfall.ll | 9 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 10 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] 11 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] 12 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] 15 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] 16 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] 19 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] 20 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] 39 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 40 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 28 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 52 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 238 ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] [all …]
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H A D | image-sample-waterfall.ll | 9 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 10 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] 11 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] 12 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] 15 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] 16 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] 19 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] 20 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] 41 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 42 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 28 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 52 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 238 ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] [all …]
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H A D | image-sample-waterfall.ll | 9 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 10 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] 11 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] 12 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] 15 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] 16 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] 19 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] 20 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] 41 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 42 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 28 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 52 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 238 ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] [all …]
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H A D | image-sample-waterfall.ll | 9 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 10 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] 11 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] 12 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] 15 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] 16 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] 19 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] 20 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] 41 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 42 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 32 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 54 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 248 ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] [all …]
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H A D | image-sample-waterfall.ll | 9 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 10 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] 11 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] 12 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] 15 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] 16 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] 19 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] 20 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] 39 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 40 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 28 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 52 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 238 ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] [all …]
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H A D | image-sample-waterfall.ll | 9 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 10 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] 11 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] 12 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] 15 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] 16 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] 19 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] 20 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] 41 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 42 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 32 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 54 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 248 ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] [all …]
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H A D | image-sample-waterfall.ll | 9 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 10 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] 11 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] 12 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] 15 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] 16 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] 19 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] 20 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] 39 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 40 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 11 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 12 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 13 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 14 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 28 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 29 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v[[VRSRC1:[0-9]+]] 30 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v[[VRSRC2:[0-9]+]] 31 ; W32-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v[[VRSRC3:[0-9]+]] 52 ; W64-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v[[VRSRC0:[0-9]+]] 238 ; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]] [all …]
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H A D | image-sample-waterfall.ll | 9 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 10 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] 11 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG2:[0-9]+]], v[[VREG2:[0-9]+]] 12 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG3:[0-9]+]], v[[VREG3:[0-9]+]] 15 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG4:[0-9]+]], v[[VREG4:[0-9]+]] 16 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG5:[0-9]+]], v[[VREG5:[0-9]+]] 19 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG6:[0-9]+]], v[[VREG6:[0-9]+]] 20 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG7:[0-9]+]], v[[VREG7:[0-9]+]] 41 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG0:[0-9]+]], v[[VREG0:[0-9]+]] 42 ; GCN-NEXT: v_readfirstlane_b32 s[[SREG1:[0-9]+]], v[[VREG1:[0-9]+]] [all …]
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/ |
H A D | mubuf-legalize-operands.ll | 9 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 10 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 11 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 12 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 32 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v0 33 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v1 34 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC2:[0-9]+]], v2 35 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC3:[0-9]+]], v3 50 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC0:[0-9]+]], v4 51 ; CHECK-DAG: v_readfirstlane_b32 s[[SRSRC1:[0-9]+]], v5 [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.abs.ll | 63 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 70 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 81 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 88 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 102 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 103 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1 113 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 114 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1 131 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 132 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.abs.ll | 63 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 70 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 81 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 88 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 102 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 103 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1 113 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 114 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1 131 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 132 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.abs.ll | 63 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 70 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 81 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 88 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 102 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 103 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1 113 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0 114 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1 131 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0 132 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1 [all …]
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