| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 415 ; GCN: v_readlane_b32 s4, v0, 48
416 ; GCN-NEXT: v_readlane_b32 s5, v0, 49
417 ; GCN-NEXT: v_readlane_b32 s6, v0, 50
418 ; GCN-NEXT: v_readlane_b32 s7, v0, 51
419 ; GCN-NEXT: v_readlane_b32 s8, v0, 52
420 ; GCN-NEXT: v_readlane_b32 s9, v0, 53
421 ; GCN-NEXT: v_readlane_b32 s10, v0, 54
422 ; GCN-NEXT: v_readlane_b32 s11, v0, 55
423 ; GCN-NEXT: v_readlane_b32 s12, v0, 56
424 ; GCN-NEXT: v_readlane_b32 s13, v0, 57
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 415 ; GCN: v_readlane_b32 s4, v0, 48
416 ; GCN-NEXT: v_readlane_b32 s5, v0, 49
417 ; GCN-NEXT: v_readlane_b32 s6, v0, 50
418 ; GCN-NEXT: v_readlane_b32 s7, v0, 51
419 ; GCN-NEXT: v_readlane_b32 s8, v0, 52
420 ; GCN-NEXT: v_readlane_b32 s9, v0, 53
421 ; GCN-NEXT: v_readlane_b32 s10, v0, 54
422 ; GCN-NEXT: v_readlane_b32 s11, v0, 55
423 ; GCN-NEXT: v_readlane_b32 s12, v0, 56
424 ; GCN-NEXT: v_readlane_b32 s13, v0, 57
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 415 ; GCN: v_readlane_b32 s4, v0, 48
416 ; GCN-NEXT: v_readlane_b32 s5, v0, 49
417 ; GCN-NEXT: v_readlane_b32 s6, v0, 50
418 ; GCN-NEXT: v_readlane_b32 s7, v0, 51
419 ; GCN-NEXT: v_readlane_b32 s8, v0, 52
420 ; GCN-NEXT: v_readlane_b32 s9, v0, 53
421 ; GCN-NEXT: v_readlane_b32 s10, v0, 54
422 ; GCN-NEXT: v_readlane_b32 s11, v0, 55
423 ; GCN-NEXT: v_readlane_b32 s12, v0, 56
424 ; GCN-NEXT: v_readlane_b32 s13, v0, 57
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 415 ; GCN: v_readlane_b32 s4, v0, 48
416 ; GCN-NEXT: v_readlane_b32 s5, v0, 49
417 ; GCN-NEXT: v_readlane_b32 s6, v0, 50
418 ; GCN-NEXT: v_readlane_b32 s7, v0, 51
419 ; GCN-NEXT: v_readlane_b32 s8, v0, 52
420 ; GCN-NEXT: v_readlane_b32 s9, v0, 53
421 ; GCN-NEXT: v_readlane_b32 s10, v0, 54
422 ; GCN-NEXT: v_readlane_b32 s11, v0, 55
423 ; GCN-NEXT: v_readlane_b32 s12, v0, 56
424 ; GCN-NEXT: v_readlane_b32 s13, v0, 57
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 125 ; GCN-NEXT: v_readlane_b32 s9, v0, 0
209 ; GCN-NEXT: v_readlane_b32 s0, v0, 1
210 ; GCN-NEXT: v_readlane_b32 s1, v0, 2
211 ; GCN-NEXT: v_readlane_b32 s2, v0, 3
212 ; GCN-NEXT: v_readlane_b32 s3, v0, 4
213 ; GCN-NEXT: v_readlane_b32 s4, v0, 5
214 ; GCN-NEXT: v_readlane_b32 s5, v0, 6
215 ; GCN-NEXT: v_readlane_b32 s6, v0, 7
216 ; GCN-NEXT: v_readlane_b32 s7, v0, 8
227 ; GCN-NEXT: v_readlane_b32 s7, v1, 0
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 287 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
288 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
289 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
290 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
291 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
292 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
293 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
294 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
298 ; GCN-NEXT: v_readlane_b32 s0, v0, 8
299 ; GCN-NEXT: v_readlane_b32 s1, v0, 9
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 287 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
288 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
289 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
290 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
291 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
292 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
293 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
294 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
298 ; GCN-NEXT: v_readlane_b32 s0, v0, 8
299 ; GCN-NEXT: v_readlane_b32 s1, v0, 9
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 287 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
288 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
289 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
290 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
291 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
292 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
293 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
294 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
298 ; GCN-NEXT: v_readlane_b32 s0, v0, 8
299 ; GCN-NEXT: v_readlane_b32 s1, v0, 9
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 287 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
288 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
289 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
290 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
291 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
292 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
293 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
294 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
298 ; GCN-NEXT: v_readlane_b32 s0, v0, 8
299 ; GCN-NEXT: v_readlane_b32 s1, v0, 9
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 287 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
288 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
289 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
290 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
291 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
292 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
293 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
294 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
298 ; GCN-NEXT: v_readlane_b32 s0, v0, 8
299 ; GCN-NEXT: v_readlane_b32 s1, v0, 9
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 287 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
288 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
289 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
290 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
291 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
292 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
293 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
294 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
298 ; GCN-NEXT: v_readlane_b32 s0, v0, 8
299 ; GCN-NEXT: v_readlane_b32 s1, v0, 9
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 287 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
288 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
289 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
290 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
291 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
292 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
293 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
294 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
298 ; GCN-NEXT: v_readlane_b32 s0, v0, 8
299 ; GCN-NEXT: v_readlane_b32 s1, v0, 9
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 207 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
208 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
209 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
210 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
211 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
212 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
213 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
214 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
229 ; GCN-NEXT: v_readlane_b32 s0, v1, 0
230 ; GCN-NEXT: v_readlane_b32 s1, v1, 1
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 287 ; GCN-NEXT: v_readlane_b32 s0, v0, 0
288 ; GCN-NEXT: v_readlane_b32 s1, v0, 1
289 ; GCN-NEXT: v_readlane_b32 s2, v0, 2
290 ; GCN-NEXT: v_readlane_b32 s3, v0, 3
291 ; GCN-NEXT: v_readlane_b32 s4, v0, 4
292 ; GCN-NEXT: v_readlane_b32 s5, v0, 5
293 ; GCN-NEXT: v_readlane_b32 s6, v0, 6
294 ; GCN-NEXT: v_readlane_b32 s7, v0, 7
298 ; GCN-NEXT: v_readlane_b32 s0, v0, 8
299 ; GCN-NEXT: v_readlane_b32 s1, v0, 9
[all …]
|
| H A D | spill-wide-sgpr.ll | 10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
38 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
39 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
40 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
100 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/ |
| H A D | partial-sgpr-to-vgpr-spills.ll | 416 ; GCN: v_readlane_b32 s4, v0, 50
417 ; GCN-NEXT: v_readlane_b32 s5, v0, 51
418 ; GCN-NEXT: v_readlane_b32 s6, v0, 52
419 ; GCN-NEXT: v_readlane_b32 s7, v0, 53
420 ; GCN-NEXT: v_readlane_b32 s8, v0, 54
421 ; GCN-NEXT: v_readlane_b32 s9, v0, 55
422 ; GCN-NEXT: v_readlane_b32 s10, v0, 56
430 ; GCN-NEXT: v_readlane_b32 s18, v1, 0
431 ; GCN-NEXT: v_readlane_b32 s19, v1, 1
607 ; GCN: v_readlane_b32 s0, v23, 32
[all …]
|