/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 25 ; GCN: v_writelane_b32 v0, s4, 0 26 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 27 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 28 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 29 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 30 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 31 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 32 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 40 ; GCN-NEXT: v_writelane_b32 v0, s9, 13 85 ; GCN: v_writelane_b32 v0, s12, 48 [all …]
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 25 ; GCN: v_writelane_b32 v0, s4, 0 26 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 27 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 28 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 29 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 30 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 31 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 32 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 40 ; GCN-NEXT: v_writelane_b32 v0, s9, 13 85 ; GCN: v_writelane_b32 v0, s12, 48 [all …]
|
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 25 ; GCN: v_writelane_b32 v0, s4, 0 26 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 27 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 28 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 29 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 30 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 31 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 32 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 40 ; GCN-NEXT: v_writelane_b32 v0, s9, 13 85 ; GCN: v_writelane_b32 v0, s12, 48 [all …]
|
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 25 ; GCN: v_writelane_b32 v0, s4, 0 26 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 27 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 28 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 29 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 30 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 31 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 32 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 40 ; GCN-NEXT: v_writelane_b32 v0, s9, 13 85 ; GCN: v_writelane_b32 v0, s12, 48 [all …]
|
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 46 ; GCN-NEXT: v_writelane_b32 v0, s0, 0 47 ; GCN-NEXT: v_writelane_b32 v0, s4, 1 48 ; GCN-NEXT: v_writelane_b32 v0, s5, 2 49 ; GCN-NEXT: v_writelane_b32 v0, s6, 3 50 ; GCN-NEXT: v_writelane_b32 v0, s7, 4 51 ; GCN-NEXT: v_writelane_b32 v0, s8, 5 52 ; GCN-NEXT: v_writelane_b32 v0, s9, 6 53 ; GCN-NEXT: v_writelane_b32 v0, s10, 7 54 ; GCN-NEXT: v_writelane_b32 v0, s11, 8 58 ; GCN-NEXT: v_writelane_b32 v0, s0, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 45 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 46 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 47 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 48 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 49 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 50 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 51 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 52 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 56 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 57 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 18 ; GCN-NEXT: v_writelane_b32 v0, s4, 0 19 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 20 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 21 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 22 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 23 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 24 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 25 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 29 ; GCN-NEXT: v_writelane_b32 v0, s4, 8 30 ; GCN-NEXT: v_writelane_b32 v0, s5, 9 [all …]
|
H A D | spill-wide-sgpr.ll | 6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 63 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1 64 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2 65 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3 93 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0 [all …]
|
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/ |
H A D | partial-sgpr-to-vgpr-spills.ll | 25 ; GCN: v_writelane_b32 v0, s4, 0 26 ; GCN-NEXT: v_writelane_b32 v0, s5, 1 27 ; GCN-NEXT: v_writelane_b32 v0, s6, 2 28 ; GCN-NEXT: v_writelane_b32 v0, s7, 3 29 ; GCN-NEXT: v_writelane_b32 v0, s8, 4 30 ; GCN-NEXT: v_writelane_b32 v0, s9, 5 31 ; GCN-NEXT: v_writelane_b32 v0, s10, 6 32 ; GCN-NEXT: v_writelane_b32 v0, s11, 7 40 ; GCN-NEXT: v_writelane_b32 v0, s9, 13 50 ; GCN-NEXT: v_writelane_b32 v0, s9, 21 [all …]
|