/dports/devel/orc/orc-0.4.31/orc/ |
H A D | orcemulateopcodes.c | 60 orc_int8 var32; in emulate_absb() local 85 orc_int8 var32; in emulate_addb() local 114 orc_int8 var32; in emulate_addssb() local 143 orc_int8 var32; in emulate_addusb() local 172 orc_int8 var32; in emulate_andb() local 201 orc_int8 var32; in emulate_andnb() local 230 orc_int8 var32; in emulate_avgsb() local 259 orc_int8 var32; in emulate_avgub() local 288 orc_int8 var32; in emulate_cmpeqb() local 317 orc_int8 var32; in emulate_cmpgtsb() local [all …]
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/dports/lang/sdcc/sdcc-4.0.0/support/regression/tests/ |
H A D | bug-2188.c | 41 int32_t var32 = notinlined_fnc(inline_fnc(0)); in testBug() local 42 ASSERT(var32 == glob_var32_a); in testBug() 43 var32 = notinlined_fnc(inline_fnc(1)); in testBug() 44 ASSERT(var32 == glob_var32_b); in testBug() 46 var32 = notinlined_ptr_fnc(inline_ptr_fnc(0)); in testBug() 47 ASSERT(var32 == glob_var32_a); in testBug() 48 var32 = notinlined_ptr_fnc(inline_ptr_fnc(1)); in testBug() 49 ASSERT(var32 == glob_var32_b); in testBug()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
H A D | atomic-ops-lse.ll | 13 @var32 = global i32 0 47 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 73 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 123 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 149 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 225 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 275 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 301 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 351 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 [all …]
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H A D | addsub-shifted.ll | 6 @var32 = global i32 0 12 %rhs1 = load volatile i32, i32* @var32 15 store volatile i32 %val1, i32* @var32 18 %rhs2 = load volatile i32, i32* @var32 21 store volatile i32 %val2, i32* @var32 24 %rhs3 = load volatile i32, i32* @var32 27 store volatile i32 %val3, i32* @var32 31 %rhs4 = load volatile i32, i32* @var32 34 store volatile i32 %val4, i32* @var32 205 store volatile i32 %v, i32* @var32 [all …]
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H A D | dp1.ll | 4 @var32 = global i32 0 11 %val0_tmp = load i32, i32* @var32 15 store volatile i32 %val1_tmp, i32* @var32 46 %val0_tmp = load i32, i32* @var32 52 store volatile i32 %val4_tmp, i32* @var32 58 %val0_tmp = load i32, i32* @var32 61 store volatile i32 %val4_tmp, i32* @var32 76 %val0_tmp = load i32, i32* @var32 94 %val0_tmp = load i32, i32* @var32 114 %val0_tmp = load i32, i32* @var32 [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/ |
H A D | atomic-ops-lse.ll | 13 @var32 = global i32 0 47 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 73 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 123 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 149 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 225 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 275 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 301 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 351 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 [all …]
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H A D | dp1.ll | 4 @var32 = global i32 0 11 %val0_tmp = load i32, i32* @var32 15 store volatile i32 %val1_tmp, i32* @var32 46 %val0_tmp = load i32, i32* @var32 52 store volatile i32 %val4_tmp, i32* @var32 58 %val0_tmp = load i32, i32* @var32 61 store volatile i32 %val4_tmp, i32* @var32 76 %val0_tmp = load i32, i32* @var32 94 %val0_tmp = load i32, i32* @var32 114 %val0_tmp = load i32, i32* @var32 [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/ |
H A D | atomic-ops-lse.ll | 13 @var32 = global i32 0 47 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 73 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 123 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 149 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 225 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 275 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 301 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 351 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/ |
H A D | atomic-ops-lse.ll | 13 @var32 = global i32 0 47 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 73 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 123 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 149 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 225 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 275 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 301 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 351 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/ |
H A D | atomic-ops-lse.ll | 13 @var32 = global i32 0 47 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 73 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 123 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 149 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 225 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 275 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 301 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 351 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AArch64/ |
H A D | atomic-ops-lse.ll | 13 @var32 = global i32 0 47 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 73 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 123 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 149 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 225 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 275 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 301 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 351 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 [all …]
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H A D | addsub-shifted.ll | 3 @var32 = global i32 0 9 %rhs1 = load volatile i32, i32* @var32 12 store volatile i32 %val1, i32* @var32 15 %rhs2 = load volatile i32, i32* @var32 18 store volatile i32 %val2, i32* @var32 21 %rhs3 = load volatile i32, i32* @var32 24 store volatile i32 %val3, i32* @var32 28 %rhs4 = load volatile i32, i32* @var32 31 store volatile i32 %val4, i32* @var32 202 store volatile i32 %v, i32* @var32 [all …]
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AArch64/ |
H A D | atomic-ops-lse.ll | 13 @var32 = global i32 0 47 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 73 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 123 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 149 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 225 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 275 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 301 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 351 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 [all …]
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H A D | dp1.ll | 3 @var32 = global i32 0 8 %val0_tmp = load i32, i32* @var32 11 store volatile i32 %val1_tmp, i32* @var32 39 %val0_tmp = load i32, i32* @var32 45 store volatile i32 %val4_tmp, i32* @var32 51 %val0_tmp = load i32, i32* @var32 54 store volatile i32 %val4_tmp, i32* @var32 69 %val0_tmp = load i32, i32* @var32 87 %val0_tmp = load i32, i32* @var32 107 %val0_tmp = load i32, i32* @var32 [all …]
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H A D | addsub-shifted.ll | 3 @var32 = global i32 0 9 %rhs1 = load volatile i32, i32* @var32 12 store volatile i32 %val1, i32* @var32 15 %rhs2 = load volatile i32, i32* @var32 18 store volatile i32 %val2, i32* @var32 21 %rhs3 = load volatile i32, i32* @var32 24 store volatile i32 %val3, i32* @var32 28 %rhs4 = load volatile i32, i32* @var32 31 store volatile i32 %val4, i32* @var32 202 store volatile i32 %v, i32* @var32 [all …]
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AArch64/ |
H A D | atomic-ops-lse.ll | 13 @var32 = global i32 0 47 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 73 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 123 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 149 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 225 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 275 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 301 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 351 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 [all …]
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H A D | dp1.ll | 3 @var32 = global i32 0 8 %val0_tmp = load i32, i32* @var32 11 store volatile i32 %val1_tmp, i32* @var32 39 %val0_tmp = load i32, i32* @var32 45 store volatile i32 %val4_tmp, i32* @var32 51 %val0_tmp = load i32, i32* @var32 54 store volatile i32 %val4_tmp, i32* @var32 69 %val0_tmp = load i32, i32* @var32 87 %val0_tmp = load i32, i32* @var32 107 %val0_tmp = load i32, i32* @var32 [all …]
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H A D | addsub-shifted.ll | 3 @var32 = global i32 0 9 %rhs1 = load volatile i32, i32* @var32 12 store volatile i32 %val1, i32* @var32 15 %rhs2 = load volatile i32, i32* @var32 18 store volatile i32 %val2, i32* @var32 21 %rhs3 = load volatile i32, i32* @var32 24 store volatile i32 %val3, i32* @var32 28 %rhs4 = load volatile i32, i32* @var32 31 store volatile i32 %val4, i32* @var32 202 store volatile i32 %v, i32* @var32 [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | addsub-shifted.ll | 6 @var32 = global i32 0 12 %rhs1 = load volatile i32, i32* @var32 15 store volatile i32 %val1, i32* @var32 18 %rhs2 = load volatile i32, i32* @var32 21 store volatile i32 %val2, i32* @var32 24 %rhs3 = load volatile i32, i32* @var32 27 store volatile i32 %val3, i32* @var32 31 %rhs4 = load volatile i32, i32* @var32 34 store volatile i32 %val4, i32* @var32 205 store volatile i32 %v, i32* @var32 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
H A D | addsub-shifted.ll | 6 @var32 = global i32 0 12 %rhs1 = load volatile i32, i32* @var32 15 store volatile i32 %val1, i32* @var32 18 %rhs2 = load volatile i32, i32* @var32 21 store volatile i32 %val2, i32* @var32 24 %rhs3 = load volatile i32, i32* @var32 27 store volatile i32 %val3, i32* @var32 31 %rhs4 = load volatile i32, i32* @var32 34 store volatile i32 %val4, i32* @var32 205 store volatile i32 %v, i32* @var32 [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | addsub-shifted.ll | 6 @var32 = global i32 0 12 %rhs1 = load volatile i32, i32* @var32 15 store volatile i32 %val1, i32* @var32 18 %rhs2 = load volatile i32, i32* @var32 21 store volatile i32 %val2, i32* @var32 24 %rhs3 = load volatile i32, i32* @var32 27 store volatile i32 %val3, i32* @var32 31 %rhs4 = load volatile i32, i32* @var32 34 store volatile i32 %val4, i32* @var32 205 store volatile i32 %v, i32* @var32 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/ |
H A D | addsub-shifted.ll | 6 @var32 = global i32 0 12 %rhs1 = load volatile i32, i32* @var32 15 store volatile i32 %val1, i32* @var32 18 %rhs2 = load volatile i32, i32* @var32 21 store volatile i32 %val2, i32* @var32 24 %rhs3 = load volatile i32, i32* @var32 27 store volatile i32 %val3, i32* @var32 31 %rhs4 = load volatile i32, i32* @var32 34 store volatile i32 %val4, i32* @var32 205 store volatile i32 %v, i32* @var32 [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | addsub-shifted.ll | 6 @var32 = global i32 0 12 %rhs1 = load volatile i32, i32* @var32 15 store volatile i32 %val1, i32* @var32 18 %rhs2 = load volatile i32, i32* @var32 21 store volatile i32 %val2, i32* @var32 24 %rhs3 = load volatile i32, i32* @var32 27 store volatile i32 %val3, i32* @var32 31 %rhs4 = load volatile i32, i32* @var32 34 store volatile i32 %val4, i32* @var32 205 store volatile i32 %v, i32* @var32 [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | addsub-shifted.ll | 6 @var32 = global i32 0 12 %rhs1 = load volatile i32, i32* @var32 15 store volatile i32 %val1, i32* @var32 18 %rhs2 = load volatile i32, i32* @var32 21 store volatile i32 %val2, i32* @var32 24 %rhs3 = load volatile i32, i32* @var32 27 store volatile i32 %val3, i32* @var32 31 %rhs4 = load volatile i32, i32* @var32 34 store volatile i32 %val4, i32* @var32 205 store volatile i32 %v, i32* @var32 [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
H A D | addsub-shifted.ll | 6 @var32 = global i32 0 12 %rhs1 = load volatile i32, i32* @var32 15 store volatile i32 %val1, i32* @var32 18 %rhs2 = load volatile i32, i32* @var32 21 store volatile i32 %val2, i32* @var32 24 %rhs3 = load volatile i32, i32* @var32 27 store volatile i32 %val3, i32* @var32 31 %rhs4 = load volatile i32, i32* @var32 34 store volatile i32 %val4, i32* @var32 205 store volatile i32 %v, i32* @var32 [all …]
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