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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
H A Darm64-code-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
H A Darm64-code-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
H A Darm64-code-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = dso_local global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
H A Delf-globals-static.ll4 @var8 = external dso_local global i8, align 1
10 %val = load i8, i8* @var8, align 1
11 store i8 %new, i8* @var8
14 ; CHECK: adrp x[[HIREG:[0-9]+]], var8
15 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
16 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
19 ; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
20 ; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
24 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
25 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = dso_local global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
H A Delf-globals-static.ll4 @var8 = external dso_local global i8, align 1
10 %val = load i8, i8* @var8, align 1
11 store i8 %new, i8* @var8
14 ; CHECK: adrp x[[HIREG:[0-9]+]], var8
15 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
16 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
19 ; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
20 ; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
24 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
25 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = dso_local global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = dso_local global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
H A Delf-globals-static.ll4 @var8 = external dso_local global i8, align 1
10 %val = load i8, i8* @var8, align 1
11 store i8 %new, i8* @var8
14 ; CHECK: adrp x[[HIREG:[0-9]+]], var8
15 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
16 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
19 ; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
20 ; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
24 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
25 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = dso_local global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
H A Delf-globals-static.ll4 @var8 = external dso_local global i8, align 1
10 %val = load i8, i8* @var8, align 1
11 store i8 %new, i8* @var8
14 ; CHECK: adrp x[[HIREG:[0-9]+]], var8
15 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
16 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
19 ; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
20 ; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
24 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
25 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = dso_local global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dcode-model-large-abs.ll3 @var8 = dso_local global i8 0
10 ret i8* @var8
12 ; CHECK: movz x0, #:abs_g0_nc:var8
13 ; CHECK: movk x0, #:abs_g1_nc:var8
14 ; CHECK: movk x0, #:abs_g2_nc:var8
15 ; CHECK: movk x0, #:abs_g3:var8
21 %val = load i8, i8* @var8
23 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var8
24 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
25 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
[all …]
H A Delf-globals-static.ll4 @var8 = external dso_local global i8, align 1
10 %val = load i8, i8* @var8, align 1
11 store i8 %new, i8* @var8
14 ; CHECK: adrp x[[HIREG:[0-9]+]], var8
15 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
16 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
19 ; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
20 ; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
24 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
25 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
/dports/emulators/qemu/qemu-6.2.0/meson/test cases/common/241 set and get variable/
H A Dmeson.build32 var8 = get_variable('var4') variable
34 set_variable('var0', get_variable('var8'))
39 assert(not is_disabler(var8))
42 assert(not is_disabler(get_variable('var0', var8)))
43 assert(not is_disabler(get_variable('----', var8)))
44 assert(not is_disabler(get_variable('----', [var8])))
45 assert(not is_disabler(get_variable('----', {'asd': var8})))
/dports/devel/meson/meson-0.60.3/test cases/common/241 set and get variable/
H A Dmeson.build32 var8 = get_variable('var4') variable
34 set_variable('var0', get_variable('var8'))
39 assert(not is_disabler(var8))
42 assert(not is_disabler(get_variable('var0', var8)))
43 assert(not is_disabler(get_variable('----', var8)))
44 assert(not is_disabler(get_variable('----', [var8])))
45 assert(not is_disabler(get_variable('----', {'asd': var8})))

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