| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vfmash_lane_f16_1.c | 124 ret = vfmsh_laneq_f16 (src1[N], src2[N], VECT_VAR (vsrc3, float, 16, 8), N);\ in exec_vfmash_lane_f16()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 339 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 341 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 339 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 339 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 333 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|
| /dports/devel/llvm11/llvm-11.0.1.src/tools/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 333 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 339 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 339 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/clang/test/CodeGen/ |
| H A D | aarch64-v8.2a-neon-intrinsics-constrained.c | 339 return vfmsh_laneq_f16(a, b, c, 7); in test_vfmsh_laneq_f16()
|