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/dports/editors/emacs-devel/emacs-4d1968b/doc/misc/
H A Dvhdl-mode.texi179 2: begin
211 @code{begin} keyword on line 2.
266 2: begin
303 @vindex vhdl-echo-syntactic-information-p
304 @vindex echo-syntactic-information-p @r{(vhdl-)}
307 @code{vhdl-echo-syntactic-information-p} to non-@code{nil} so that the
398 2: begin
411 2: begin
457 2: begin
803 line begins with a @code{begin} or @code{end} keyword, the syntactic
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/dports/editors/emacs/emacs-27.2/doc/misc/
H A Dvhdl-mode.texi179 2: begin
211 @code{begin} keyword on line 2.
266 2: begin
303 @vindex vhdl-echo-syntactic-information-p
304 @vindex echo-syntactic-information-p @r{(vhdl-)}
307 @code{vhdl-echo-syntactic-information-p} to non-@code{nil} so that the
398 2: begin
411 2: begin
457 2: begin
803 line begins with a @code{begin} or @code{end} keyword, the syntactic
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/dports/cad/freehdl/freehdl-0.0.7/v2cc/
H A Dadder.vhdl10 -- "gvhdl -c adder.vhdl"
24 begin
25 p: process (a,b) process
28 begin
H A Dtop.vhdl10 -- "gvhdl top.vhdl adder.o ../ieee/std_logic_1164.o
30 begin
41 p: process (clk) process
42 begin
/dports/cad/geda/geda-gaf-1.8.2/gnetlist/scheme/
H A Dgnet-vhdl.scm139 (begin
148 (begin
170 (begin
262 (begin
321 (begin
334 (begin
445 (begin
448 (begin
517 (begin
580 (begin
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/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue1051/
H A Dpsi_tb_txt_util.vhd27 ---- File name: txt_util.vhdl ----
156 begin
165 begin
174 begin
192 begin
204 begin
215 begin
227 -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
274 -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
406 when 'p' => u:='P';
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/dports/cad/yosys/yosys-yosys-0.12/manual/
H A DPRESENTATION_Prog.tex4 \begin{frame}
13 \begin{center}
18 \node[process, dashed, fill=green!5] (vhdl) [right of=vlog] {VHDL Frontend};
19 \node[process] (ilang) [right of=vhdl] {Other Frontends};
29 \draw[-latex] (vhdl) -- (ast);
51 \begin{center}
78 \begin{center}
107 \begin{itemize}
130 \begin{itemize}
211 \hfil\begin{tabular}{p{3cm}l}
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/dports/editors/jed/jed-0.99-19/lib/
H A Dvhdlmode.sl3 % This is a simple vhdl mode. First it implements a highlighting scheme.
60 else if (looking_at("begin"))
65 % else if (looking_at("begin"))
88 % if (looking_at("begin"))
132 variable p, cont;
/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/
H A Dstd_logic_1164-body.proto1 -- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
42 begin
57 begin
74 begin
104 begin
111 begin
133 begin
164 begin
199 begin
205 begin
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/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/v08/
H A Dstd_logic_1164-body.vhdl1 -- This -*- vhdl -*- file was generated from std_logic_1164-body.proto
2 -- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
1001 p := l'left;
1026 p := p + dir;
1065 p := l'left;
1082 p := p + dir;
1136 p := p + dir;
1191 p := p + dir;
1256 p := p + dir;
1311 p := p + dir;
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/dports/editors/emacs-devel/emacs-4d1968b/lisp/
H A DChangeLog.102723 (ps-begin-page): Code fix.
3311 subtypes, begin blocks, etc.).
4868 (ps-begin-file): Code fix.
5019 (vhdl-template-generate-body): Remove "begin" for VHDL'93.
5026 (vhdl-sequential-statement-p): Better algorithm.
5072 (vhdl-project-p, vhdl-re-search-backward, vhdl-re-search-forward)
5105 (vhdl-in-comment-p, vhdl-in-string-p, vhdl-standard-p): Define as
5107 (vhdl-in-comment-or-string-p, vhdl-speedbar-project-p):
5560 (ps-begin-file, ps-begin-job): ps-default-fg and ps-default-bg
11339 (vhdl-corresponding-begin): Likewise.
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H A DChangeLog.171511 (vhdl-in-comment-p, vhdl-in-literal, vhdl-win-il)
1516 (vhdl-libunit-re, vhdl-defun-re, vhdl-begin-p)
1517 (vhdl-corresponding-begin, vhdl-get-library-unit, vhdl-regress-line)
4351 * progmodes/verilog-mode.el (verilog-no-indent-begin-re):
4352 Fix `verilog-indent-begin-after-if' nil not honoring 'forever',
4365 (vhdl-asort, vhdl-anot-head-p): Remove.
6814 (verilog-no-indent-begin-re): When `verilog-indent-begin-after-if'
7041 (c-ssb-lit-begin): Remove unused var `pps-end-pos'.
11715 (vhdl-asort, vhdl-anot-head-p, vhdl-aput, vhdl-adelete, vhdl-aget):
14434 syntax-begin-function (bug#16247).
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H A DChangeLog.12117 (vhdl-template-break, vhdl-regress-line, vhdl-electric-tab):
1798 (ps-begin-job): Adjust calls to it appropriately.
1837 (ispell-begin-skip-region-regexp): Fix typos in docstrings.
2011 (ps-begin-job): New arg. Fix ps-default-background and
2255 (vhdl-get-library-unit, vhdl-corresponding-begin)
4242 (ada-goto-matching-start): Handle nested `begin ... end'.
8729 (gdb-frame-begin): Set gdb-frame-begin, gdb-printing.
22060 (vhdl-end-p): Fix indentation bug "else" after "-- when".
22506 * emerge.el (merge-begin, merge-end, template, A-begin, A-end)
30381 (ps-mule-begin-job): Call find-charset-region/string with
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H A DChangeLog.84952 * progmodes/vhdl-mode.el (vhdl-port-copy): Fix parsing bug.
7729 (ps-mule-begin-job): Rename from ps-mule-begin.
8635 (ps-mule-get-font-spec, ps-mule-begin, ps-begin-file)
8663 (ps-mule-initialize, ps-mule-begin, ps-face-bold-p, ps-do-despool):
8905 * progmodes/vhdl-mode.el
8907 (vhdl-template-assert, vhdl-block, vhdl-configuration-spec)
8908 (vhdl-elsif, vhdl-generate, vhdl-if, vhdl-map)
8909 (vhdl-selected-signal-assignment, vhdl-use, vhdl-while-loop)
8910 (vhdl-get-port, vhdl-get-generic): Replace (undo 0) by (undo).
8913 (vhdl-get-port, vhdl-get-generic): Bug fix in template.
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/dports/editors/emacs/emacs-27.2/lisp/
H A DChangeLog.102723 (ps-begin-page): Code fix.
3311 subtypes, begin blocks, etc.).
4868 (ps-begin-file): Code fix.
5019 (vhdl-template-generate-body): Remove "begin" for VHDL'93.
5026 (vhdl-sequential-statement-p): Better algorithm.
5072 (vhdl-project-p, vhdl-re-search-backward, vhdl-re-search-forward)
5105 (vhdl-in-comment-p, vhdl-in-string-p, vhdl-standard-p): Define as
5107 (vhdl-in-comment-or-string-p, vhdl-speedbar-project-p):
5560 (ps-begin-file, ps-begin-job): ps-default-fg and ps-default-bg
11339 (vhdl-corresponding-begin): Likewise.
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H A DChangeLog.171511 (vhdl-in-comment-p, vhdl-in-literal, vhdl-win-il)
1516 (vhdl-libunit-re, vhdl-defun-re, vhdl-begin-p)
1517 (vhdl-corresponding-begin, vhdl-get-library-unit, vhdl-regress-line)
4351 * progmodes/verilog-mode.el (verilog-no-indent-begin-re):
4352 Fix `verilog-indent-begin-after-if' nil not honoring 'forever',
4365 (vhdl-asort, vhdl-anot-head-p): Remove.
6814 (verilog-no-indent-begin-re): When `verilog-indent-begin-after-if'
7041 (c-ssb-lit-begin): Remove unused var `pps-end-pos'.
11715 (vhdl-asort, vhdl-anot-head-p, vhdl-aput, vhdl-adelete, vhdl-aget):
14434 syntax-begin-function (bug#16247).
[all …]
H A DChangeLog.12117 (vhdl-template-break, vhdl-regress-line, vhdl-electric-tab):
1798 (ps-begin-job): Adjust calls to it appropriately.
1837 (ispell-begin-skip-region-regexp): Fix typos in docstrings.
2011 (ps-begin-job): New arg. Fix ps-default-background and
2255 (vhdl-get-library-unit, vhdl-corresponding-begin)
4242 (ada-goto-matching-start): Handle nested `begin ... end'.
8729 (gdb-frame-begin): Set gdb-frame-begin, gdb-printing.
22060 (vhdl-end-p): Fix indentation bug "else" after "-- when".
22506 * emerge.el (merge-begin, merge-end, template, A-begin, A-end)
30381 (ps-mule-begin-job): Call find-charset-region/string with
[all …]
H A DChangeLog.84952 * progmodes/vhdl-mode.el (vhdl-port-copy): Fix parsing bug.
7729 (ps-mule-begin-job): Rename from ps-mule-begin.
8635 (ps-mule-get-font-spec, ps-mule-begin, ps-begin-file)
8663 (ps-mule-initialize, ps-mule-begin, ps-face-bold-p, ps-do-despool):
8905 * progmodes/vhdl-mode.el
8907 (vhdl-template-assert, vhdl-block, vhdl-configuration-spec)
8908 (vhdl-elsif, vhdl-generate, vhdl-if, vhdl-map)
8909 (vhdl-selected-signal-assignment, vhdl-use, vhdl-while-loop)
8910 (vhdl-get-port, vhdl-get-generic): Replace (undo 0) by (undo).
8913 (vhdl-get-port, vhdl-get-generic): Bug fix in template.
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/dports/editors/joe/joe-4.6/rc/
H A Dftyperc165 -text_delimiters BEGIN|Begin|begin=END|End|end
299 -text_delimiters `ifdef|`ifndef=`else=`endif:begin=end:case|casex|casez=endcase:function=endfunctio…
304 [vhdl]
307 -syntax vhdl
496 *.p
504 -text_delimiters begin|BEGIN|record|RECORD|case|CASE=end|END:repeat|REPEAT=until|UNTIL
/dports/textproc/kf5-syntax-highlighting/syntax-highlighting-5.89.0/autotests/input/
H A Dlight52_muldiv.vhdl2 -- light52_muldiv.vhdl -- Simple multiplier/divider module.
125 begin
130 begin
157 begin
214 begin
245 package p is package
256 package body p is package
260 begin
274 begin
344 begin
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/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug037/
H A Dsim_simulation.v08.vhdl108 -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
121 begin
126 begin
131 begin
136 begin
141 begin
146 begin
152 begin
424 variable p : TIME; variable
432 p := Pause;
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/dports/textproc/kf5-syntax-highlighting/syntax-highlighting-5.89.0/autotests/folding/
H A Dlight52_muldiv.vhdl.fold2 -- light52_muldiv.vhdl -- Simple multiplier/divider module.
125 begin
130 begin
157 begin
214 begin
245 package <beginfold id='6'>p</beginfold id='6'> is
256 package body <beginfold id='8'>p</beginfold id='8'> is
344 begin
349 begin
381 begin
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/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue317/PoC/src/sim/
H A Dsim_waveform.vhdl281 -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here
296 begin
309 begin
320 begin
342 begin
424 begin
454 begin
459 begin
966 variable p : time; variable
977 p := Pause;
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/dports/cad/ghdl/ghdl-1.0.0/doc/
H A Dghdl.texi885 begin
968 begin
995 begin
1020 begin
2250 begin
2295 begin
2322 begin
3264 begin
5237 begin
5247 begin
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/dports/devel/doxygen/doxygen-1.9.3/src/
H A Dutil.cpp547 bool vhdl = Config_getBool(OPTIMIZE_OUTPUT_VHDL); in removeRedundantWhiteSpace() local
549 if (s.isEmpty() || vhdl) return s; in removeRedundantWhiteSpace()
1986 auto srcIt = srcAl->begin(); in matchArguments2()
1987 auto dstIt = dstAl->begin(); in matchArguments2()
2018 auto srcIt=srcAl.begin(); in mergeArguments()
2019 auto dstIt=dstAl.begin(); in mergeArguments()
4504 actIt = actualArgs->begin(); in substituteTemplateArgumentsInString()
7181 for (p=s.data(); (q=strstr(p,begin.data()))!=0; p=q+endLen) in clearBlock()
7196 for (r=result.rawData(), p=s.data(); (q=strstr(p,begin.data()))!=0; p=q+endLen) in clearBlock()
7217 QCString begin; in selectBlock() local
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