/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/v93/ |
H A D | std_logic_1164-body.vhdl | 176 if la'length /= ra'length then 195 if la'length /= ra'length then 214 if la'length /= ra'length then 233 if la'length /= ra'length then 252 if la'length /= ra'length then 271 if la'length /= ra'length then 302 if la'length /= ra'length then 321 if la'length /= ra'length then 340 if la'length /= ra'length then 747 if std_x (s (i)) then [all …]
|
/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/v87/ |
H A D | std_logic_1164-body.vhdl | 158 if la'length /= ra'length then 177 if la'length /= ra'length then 196 if la'length /= ra'length then 215 if la'length /= ra'length then 234 if la'length /= ra'length then 265 if la'length /= ra'length then 284 if la'length /= ra'length then 303 if la'length /= ra'length then 322 if la'length /= ra'length then 691 if std_x (s (i)) then [all …]
|
/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/ |
H A D | std_logic_1164-body.proto | 1 -- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only 18 -- This is a template file. To avoid errors and duplication, the python 227 if l'ascending then 250 if l'ascending then 274 if p = l'right then 314 if l'ascending then 371 if c /= '_' then 423 if l'ascending then 488 if c /= '_' then 543 if l'ascending then [all …]
|
/dports/editors/emacs-devel/emacs-4d1968b/lisp/ |
H A D | ChangeLog.10 | 733 then template arglists will behave just like paren sexps with 4913 (vhdl-template-exit, vhdl-template-next, vhdl-template-return): 4973 (vhdl-template-field): Fix case on all VHDL words. 4974 (vhdl-template-others): Re-electrified "others". 5018 (vhdl-template-header): New argument `is-model'. 5040 (vhdl-template-architecture): Code optimization. 5042 (vhdl-template-component-decl, vhdl-port-paste-declaration): 5091 (vhdl-subprog-paste-specification, vhdl-template-others-hook) 5092 (vhdl-template-replace-header-keywords, vhdl-toggle-project) 5109 (vhdl-compose, vhdl-naming, vhdl-speedbar, vhdl-template) [all …]
|
H A D | ChangeLog.17 | 1498 (vhdl-template-construct-alist-init, vhdl-create-mode-menu): 1501 (vhdl-template-map-init): Add vhdl-template-context. 1508 (vhdl-words-init, vhdl-template-process) 1509 (vhdl-template-replace-header-keywords): Support VHDL'08. 1514 (vhdl-beginning-of-directive, vhdl-template-context) 1515 (vhdl-template-context-hook): New functions. 17206 supported by prolog-electric-if-then-else-flag. 17223 (prolog-electric--if-then-else): Rename from 17228 (prolog-electric-if-then-else): Remove commands. 24375 (vhdl-template-component-inst): Handle empty library. [all …]
|
H A D | ChangeLog.12 | 114 * progmodes/vhdl-mode.el (vhdl-template-type) 115 (vhdl-template-record, vhdl-template-nature) 116 (vhdl-template-configuration-spec, vhdl-template-component-inst) 117 (vhdl-template-break, vhdl-regress-line, vhdl-electric-tab): 10345 (grep-find-template): Rename from grep-tree-template. 14524 function we then call. 19172 and then passed in to the system. 19260 and then passed in to the system. 21522 (vhdl-hooked-abbrev, vhdl-template-insert-fun) 23663 (tempo-define-template, tempo-insert-template) [all …]
|
/dports/editors/emacs/emacs-27.2/lisp/ |
H A D | ChangeLog.10 | 733 then template arglists will behave just like paren sexps with 4913 (vhdl-template-exit, vhdl-template-next, vhdl-template-return): 4973 (vhdl-template-field): Fix case on all VHDL words. 4974 (vhdl-template-others): Re-electrified "others". 5018 (vhdl-template-header): New argument `is-model'. 5040 (vhdl-template-architecture): Code optimization. 5042 (vhdl-template-component-decl, vhdl-port-paste-declaration): 5091 (vhdl-subprog-paste-specification, vhdl-template-others-hook) 5092 (vhdl-template-replace-header-keywords, vhdl-toggle-project) 5109 (vhdl-compose, vhdl-naming, vhdl-speedbar, vhdl-template) [all …]
|
H A D | ChangeLog.17 | 1498 (vhdl-template-construct-alist-init, vhdl-create-mode-menu): 1501 (vhdl-template-map-init): Add vhdl-template-context. 1508 (vhdl-words-init, vhdl-template-process) 1509 (vhdl-template-replace-header-keywords): Support VHDL'08. 1514 (vhdl-beginning-of-directive, vhdl-template-context) 1515 (vhdl-template-context-hook): New functions. 17206 supported by prolog-electric-if-then-else-flag. 17223 (prolog-electric--if-then-else): Rename from 17228 (prolog-electric-if-then-else): Remove commands. 24375 (vhdl-template-component-inst): Handle empty library. [all …]
|
H A D | ChangeLog.12 | 114 * progmodes/vhdl-mode.el (vhdl-template-type) 115 (vhdl-template-record, vhdl-template-nature) 116 (vhdl-template-configuration-spec, vhdl-template-component-inst) 117 (vhdl-template-break, vhdl-regress-line, vhdl-electric-tab): 10345 (grep-find-template): Rename from grep-tree-template. 14524 function we then call. 19172 and then passed in to the system. 19260 and then passed in to the system. 21522 (vhdl-hooked-abbrev, vhdl-template-insert-fun) 23663 (tempo-define-template, tempo-insert-template) [all …]
|
/dports/cad/ghdl/ghdl-1.0.0/libraries/openieee/v08/ |
H A D | std_logic_1164-body.vhdl | 1 -- This -*- vhdl -*- file was generated from std_logic_1164-body.proto 19 -- This is a template file. To avoid errors and duplication, the python 518 if r >= 0 then 533 if r >= 0 then 549 if r >= 0 then 567 if r >= 0 then 973 if l'ascending then 996 if l'ascending then 1117 if c /= '_' then 1234 if c /= '_' then [all …]
|
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug019/PoC/src/common/ |
H A D | config.vhdl | 15 -- See also template file my_config.vhdl.template. 295 if (str(i) = C_POC_NUL) then 324 if (chr1 /= chr2) then 363 if (POC_VERBOSE = TRUE) then 396 if (str'length > 0) then 431 if chr_isDigit(str(i)) then 437 if (low = -1) then return 0; end if; 440 if chr_isAlpha(str(i)) then 446 if (high = -1) then return 0; end if; 679 if (1 fs /= 1 us) then [all …]
|
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug037/ |
H A D | config.vhdl | 15 -- See also template file my_config.vhdl.template. 102 if (str'length > 0) then 519 if (str(i) = C_POC_NUL) then 553 if (chr1 /= chr2) then 592 if (POC_VERBOSE = TRUE) then 617 if chr_isDigit(str(i)) then 623 if (low = -1) then return 0; end if; 626 if chr_isAlpha(str(i)) then 632 if (high = -1) then return 0; end if; 719 if (1 fs /= 1 us) then [all …]
|
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug035/ |
H A D | config.vhdl | 15 -- See also template file my_config.vhdl.template. 102 if (str'length > 0) then 519 if (str(i) = C_POC_NUL) then 553 if (chr1 /= chr2) then 592 if (POC_VERBOSE = TRUE) then 617 if chr_isDigit(str(i)) then 623 if (low = -1) then return 0; end if; 626 if chr_isAlpha(str(i)) then 632 if (high = -1) then return 0; end if; 719 if (1 fs /= 1 us) then [all …]
|
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue317/PoC/src/common/ |
H A D | config.vhdl | 14 -- See also template file my_config.vhdl.template. 101 if (str'length > 0) then 551 if str(i) = C_POC_NUL then 561 if str(i) = C_POC_NUL then 585 if chr1 /= chr2 then 624 if POC_VERBOSE then 649 if chr_isDigit(str(i)) then 655 if low = -1 then return 0; end if; 664 if high = -1 then return 0; end if; 754 if (1 fs /= 1 us) then [all …]
|
/dports/devel/doxygen/doxygen-1.9.3/doc/ |
H A D | starting.doc | 37 \section step0 Step 0: Check if doxygen supports your programming language 56 template configuration file for you. To do this call \c doxygen 65 \<config-file\>.bak before generating the configuration template. 76 You can probably leave the values of most tags in a generated template 95 patterns will be parsed (if the patterns are omitted a list of 122 .i++ |C / C++ | .php |PHP |.vhdl |VHDL 150 generate such cross-references if you set 204 will be generated. This file can then be viewed using \c xdvi or 213 Conversion to PDF is also possible if you have installed the ghostscript 313 (`*`) and then optionally more whitespace, [all …]
|
/dports/cad/ghdl/ghdl-1.0.0/doc/ |
H A D | ghdl.texi | 1853 Emit a warning if a @code{/*} appears within a block comment (vhdl 2008). 2253 if rst = '1' then 2256 if v = "1010" then -- Error 2298 if rst = '1' then 2301 if ieee.std_logic_unsigned."=" (v, "1010") then 2325 if rst = '1' then 2328 if v = "1010" then 5273 For if/then statement: 5282 if Get_Expr_Staticness (Decl) = Locally then 5286 If not possible, ‘then’ is alone on its line aligned with the ‘if’: [all …]
|
/dports/sysutils/zeitgeist/zeitgeist-1.0.3/libzeitgeist/ |
H A D | mimetype.vala | 75 * MIME-types are first looked up by their exact name and then if none is 88 if (mimetypes == null) 104 * MIME-types are first looked up by their exact name and then if none is 142 if (mimetype == null) 146 if (interpretation != null) 151 if (mime_regex.regex.match (mimetype, 0)) 197 if (uri.has_prefix (scheme.uri_scheme)) 206 if (mimetypes_loaded) 298 register_mimetype ("text/x-gettext-translation-template", NFO.SOURCE_CODE); 318 register_mimetype ("text/x-vhdl", NFO.SOURCE_CODE); [all …]
|
/dports/x11-toolkits/scintilla/scite/src/ |
H A D | Embedded.properties | 1178 keywords.$(file.patterns.ave)=nil true false else for if while then elseif end av self in exit 1182 statement.indent.$(file.patterns.ave)=1 else for if while then 3065 template this throw true try typedef typeid typeof \ 4143 if in local mod not od or quit rec repeat return then until while QUIT 4781 function if of procedure repeat then to try until uses var while with 5949 template try tuple type \ 7882 then when END case else for nil retry true while alias class elsif if \ 8206 if then else when try \ 9619 filter.vhdl=VHDL (vhd vhdl)|$(file.patterns.vhdl)| 9621 *filter.vhdl=$(filter.vhdl) [all …]
|
/dports/editors/scite/scite/src/ |
H A D | Embedded.properties | 1178 keywords.$(file.patterns.ave)=nil true false else for if while then elseif end av self in exit 1182 statement.indent.$(file.patterns.ave)=1 else for if while then 3065 template this throw true try typedef typeid typeof \ 4143 if in local mod not od or quit rec repeat return then until while QUIT 4781 function if of procedure repeat then to try until uses var while with 5949 template try tuple type \ 7882 then when END case else for nil retry true while alias class elsif if \ 8206 if then else when try \ 9619 filter.vhdl=VHDL (vhd vhdl)|$(file.patterns.vhdl)| 9621 *filter.vhdl=$(filter.vhdl) [all …]
|
/dports/cad/electric/electric-7.00/lib/international/ |
H A D | messages.po | 10125 msgid "Yes, then stop" 10160 msgid ", would add %ld wires if 'ports must match' were off" 11126 msgid "CDL template" 12266 msgid "Type 'help' if you need it" 12333 msgid "Cannot create CDL template file: %s" 15471 msgid "Can only stop execution of a macro if one is running" 20409 msgid "Library (if not in list):" 21543 msgid "This object tells if %s is a serpentine transistor" 21548 msgid "This object tells if %s is square" 25753 msgid "Highlight then &Focus" [all …]
|
/dports/databases/mongodb36/mongodb-src-r3.6.23/src/third_party/wiredtiger/src/docs/ |
H A D | Doxyfile | 27 # to put quotes around the project name if it contains spaces. 33 # if some version control system is used. 227 plantuml_end="PlantUML template end -->" \ 228 … plantuml_start{1}="\image html \1\n\image latex \1\n<!-- PlantUML template begins" \ 437 # This option has no effect if EXTRACT_ALL is enabled. 462 # The INTERNAL_DOCS tag determines if documentation 596 # Folder Tree View (if specified). The default is YES. 713 # *.f90 *.f *.for *.vhd *.vhdl 746 *.vhdl 877 # then for each documented function all documented [all …]
|
/dports/math/eigen3/eigen-3.3.9/doc/ |
H A D | Doxyfile.in | 27 # to put quotes around the project name if it contains spaces. 33 # if some version control system is used. 439 # This option has no effect if EXTRACT_ALL is enabled. 464 # The INTERNAL_DOCS tag determines if documentation 598 # Folder Tree View (if specified). The default is YES. 714 # *.f90 *.f *.for *.vhd *.vhdl 740 # the class template to not contain the template signature. This only happens 836 # filter if there is a match. 881 # then for each documented function all documented 1533 # if you want to understand what is going on. [all …]
|
/dports/math/stanmath/math-4.2.0/lib/eigen_3.3.9/doc/ |
H A D | Doxyfile.in | 27 # to put quotes around the project name if it contains spaces. 33 # if some version control system is used. 439 # This option has no effect if EXTRACT_ALL is enabled. 464 # The INTERNAL_DOCS tag determines if documentation 598 # Folder Tree View (if specified). The default is YES. 714 # *.f90 *.f *.for *.vhd *.vhdl 740 # the class template to not contain the template signature. This only happens 836 # filter if there is a match. 881 # then for each documented function all documented 1533 # if you want to understand what is going on. [all …]
|
/dports/misc/opennn/opennn-5.0.5/eigen/doc/ |
H A D | Doxyfile.in | 27 # to put quotes around the project name if it contains spaces. 33 # if some version control system is used. 439 # This option has no effect if EXTRACT_ALL is enabled. 464 # The INTERNAL_DOCS tag determines if documentation 598 # Folder Tree View (if specified). The default is YES. 714 # *.f90 *.f *.for *.vhd *.vhdl 740 # the class template to not contain the template signature. This only happens 836 # filter if there is a match. 881 # then for each documented function all documented 1533 # if you want to understand what is going on. [all …]
|
/dports/games/quakeforge/quakeforge-0.7.2/doc/ |
H A D | quakeforge.dox.conf.in | 33 # if some version control system is used. 399 # This option has no effect if EXTRACT_ALL is enabled. 424 # The INTERNAL_DOCS tag determines if documentation 558 # Folder Tree View (if specified). The default is YES. 681 # *.f90 *.f *.for *.vhd *.vhdl 711 @TOPSRC@/doc/template.dox \ 712 @TOPSRC@/doc/template.c \ 713 @TOPSRC@/doc/template.h 781 # filter if there is a match. 1476 # if you want to understand what is going on. [all …]
|