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Searched refs:vhdl_assign_stmt (Results 1 – 4 of 4) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dlogic.cc218 (new vhdl_assign_stmt(new vhdl_var_ref("UDP_Inputs", NULL), tmp_rhs)); in seq_udp_logic()
H A Dvhdl_syntax.hh412 class vhdl_assign_stmt : public vhdl_abstract_assign_stmt { class
414 vhdl_assign_stmt(vhdl_var_ref *lhs, vhdl_expr *rhs) in vhdl_assign_stmt() function in vhdl_assign_stmt
H A Dstmt.cc323 return new vhdl_assign_stmt(lhs, rhs); in assign_for()
554 container->add_stmt(new vhdl_assign_stmt(tmp_decl->make_ref(), rhs)); in make_assignment()
1069 container->add_stmt(new vhdl_assign_stmt(tmp_ref, test)); in draw_case_test()
H A Dvhdl_syntax.cc668 void vhdl_assign_stmt::emit(std::ostream &of, int level) const in emit()