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Searched refs:vhdl_const_bits (Results 1 – 6 of 6) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dcast.cc238 vhdl_expr* zeros = new vhdl_const_bits(string(newwidth - 1, '0').c_str(), in resize()
272 int64_t vhdl_const_bits::bits_to_int() const in bits_to_int()
287 vhdl_expr *vhdl_const_bits::to_std_logic() in to_std_logic()
299 char vhdl_const_bits::sign_bit() const in sign_bit()
304 vhdl_expr *vhdl_const_bits::to_vector(vhdl_type_name_t name, int w) in to_vector()
319 vhdl_expr *vhdl_const_bits::to_integer() in to_integer()
324 vhdl_expr *vhdl_const_bits::resize(int w) in resize()
352 return (new vhdl_const_bits(&bit_, 1, name == VHDL_TYPE_SIGNED))->resize(w); in to_vector()
H A Dvhdl_syntax.cc676 vhdl_const_bits::vhdl_const_bits(const char *value, int width, bool issigned, in vhdl_const_bits() function in vhdl_const_bits
695 bool vhdl_const_bits::has_meta_bits() const in has_meta_bits()
700 void vhdl_const_bits::emit(std::ostream &of, int) const in emit()
H A Dlogic.cc157 vhdl_expr *cond = new vhdl_const_bits(row, nin, false); in comb_udp_logic()
H A Dvhdl_syntax.hh189 class vhdl_const_bits : public vhdl_expr { class
191 vhdl_const_bits(const char *value, int width, bool issigned,
H A Dexpr.cc130 return new vhdl_const_bits(ivl_expr_bits(e), ivl_expr_width(e), in translate_number()
H A Dscope.cc274 new vhdl_const_bits(ivl_const_bits(con), ivl_const_width(con), in draw_nexus()